I/O Pin Exceptions; Differential I/Os; I/O Banks; I/O Pin Exceptions - Perst - Enclustra Mars XU3 User Manual

2.9.2

I/O Pin Exceptions

The I/O pin exceptions are pins with special functions or restrictions (for example, when used in combination
with certain Mars boards they may have a specific role).
PCIe Reset Signal (PERST#)
Table 6 lists the I/O pin exceptions on the Mars XU3 SoC module related to the PCIe reset connection.
I/O Name
PS_MIO42_PERST#
Table 6: I/O Pin Exceptions - PERST
The PERST# connection to module connector pin 148 is implemented for future support of PCIe interface
on Enclustra Mars base boards.
2.9.3

Differential I/Os

When using differential pairs, a differential impedance of 100
the two nets of a differential pair must have the same length.
The information regarding the length of the signal lines from the MPSoC device to the module connector is
available in Mars XU3 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the total
length of the differential pairs on the base board if required by the application.
The I/Os in the HD bank (26) can be used only as differential inputs when LVDS/LVPECL standards are used;
LVDS/LVPECL outputs are not supported.
Internal differential termination is not supported for the HD pins; differential input pairs on the module
connector may be terminated by external termination resistors on the base board (close to the module
pins).
2.9.4

I/O Banks

Table 7 describes the main attributes of the FPGA and PS I/O banks, and indicates which peripherals are
connected to each I/O bank. All I/O pins within a particular I/O bank must use the same I/O (VCC_IO) and
reference (VREF) voltages.
2
Bank
Bank 65
Bank 66
Continued on next page...
2
I2C on PL side is available starting with revision 2 modules.
D-0000-432-001
Module Connector Pin
148
Connectivity
Module connector, I2C
Module connector, Ethernet PHY
Description
Connected via a 1 k resistor to MIO pin 30 for PCIe
PERST# connection implementation
must be matched on the base board, and
2
, LEDs
17 / 52
VCC_IO VREF
User selectable
GND
VCC_IO_B65
User selectable
GND
VCC_IO_B65
Version 04, 25.07.2019