Enclustra Mercury+ XU8 SoC User Manual
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Enclustra Mercury+ XU8 SoC User Manual

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Mercury+ XU8 SoC Module
Purpose
The purpose of this document is to present the characteristics of Mercury+ XU8 SoC module to the user,
and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU8 SoC
module.
Summary
This document first gives an overview of the Mercury+ XU8 SoC module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information
Product
Document Information
Reference / Version / Date
Approval Information
Written by
Verified by
Approved by
User Manual
Code
ME-XU8
Reference
D-0000-454-001
Name
DIUN, MMOS
GKOE, RPAU
DIUN
Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland
Name
Mercury+ XU8 SoC Module
Version
07
Position
Design Engineer
Design Expert
Manager, BU SP
Phone +41 43 343 39 43 – www.enclustra.com
Date
16.02.2021
Date
03.09.2018
10.09.2018
16.02.2021

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Summary of Contents for Enclustra Mercury+ XU8 SoC

  • Page 1 Mercury+ XU8 SoC Module User Manual Purpose The purpose of this document is to present the characteristics of Mercury+ XU8 SoC module to the user, and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU8 SoC module.
  • Page 2 Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior written permission of Enclustra GmbH, Switzerland. Although Enclustra GmbH believes that the information included in this publication is correct as of the date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.

  • Page 3: Table Of Contents

    Enclustra Build Environment ........
  • Page 4 3.13 Enclustra Module Configuration Tool ........51 I2C Communication Overview .
  • Page 5 Secure EEPROM ..........53 4.4.1 Memory Map .

  • Page 6: Overview

    The Enclustra Build Environment [14] is available for the Mercury+ XU8 SoC module. This build system allows the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot Loader).

  • Page 7: Electrostatic Discharge

    Warning! It is possible to mount the Mercury+ XU8 SoC module the wrong way round on the base board - always check that the mounting holes on the base board are aligned with the mounting holes of the Mercury+ XU8 SoC module.

  • Page 8: Deliverables

    Enclustra Build Environment The Enclustra Build Environment (EBE) [14] enables the user to quickly set up and run Linux on any Enclustra SoC module or system board. It allows the user to choose the desired target, and download all the required binaries, such as bitstream and FSBL.

  • Page 9: Enclustra Heat Sink

    FMC interfaces, the compatibility of the Mercury+ XU8 SoC module to the Mercury+ PE1 base board is limited. It is recommended to check the FMC card pinout in detail with the Enclustra Mercury Master Pinout and with the module and base board schematics.

  • Page 10: Xilinx Tool Support

    Please note that the available features depend on the equipped Mercury module type. Xilinx Tool Support The MPSoC devices equipped on the Mercury+ XU8 SoC module are supported by the Vivado HL WebPACK Edition software, which is available free of charge. Please contact Xilinx for further information.

  • Page 11: Module Description

    Figure 1: Hardware Block Diagram The main component of the Mercury+ XU8 SoC module is the Xilinx Zynq Ultrascale+ MPSoC device. Most of its I/O pins are connected to the Mercury+ module connector, making 136 regular user I/Os available to the user.

  • Page 12: Module Configuration And Product Codes

    Figure 2: Product Code Fields Please note that for the first revision modules or early access modules, the product code may not respect entirely this naming convention. Please contact Enclustra for details on this aspect. D-0000-454-001 12 / 61...

  • Page 13: Article Numbers And Article Codes

    The correspondence between article number and article code is shown in Table 2. The article code repre- sents the product code, followed by the revision; the R suffix and number represent the revision number. The revision changes and product known issues are described in the Mercury+ XU8 SoC Module Known Issues and Changes document [6].

  • Page 14: Top And Bottom Views

    Top and Bottom Views 2.4.1 Top View Figure 4: Module Top View 2.4.2 Bottom View Figure 5: Module Bottom View Please note that depending on the hardware revision and configuration, the module may look slightly dif- ferent than shown in this document. D-0000-454-001 14 / 61 Version 07, 16.02.2021...

  • Page 15: Top And Bottom Assembly Drawings

    Top and Bottom Assembly Drawings 2.5.1 Top Assembly Drawing Figure 6: Module Top Assembly Drawing 2.5.2 Bottom Assembly Drawing Figure 7: Module Bottom Assembly Drawing Please note that depending on the hardware revision and configuration, the module may look slightly dif- ferent than shown in this document.

  • Page 16: Module Footprint

    Figure 8: Module Footprint - Top View Warning! It is possible to mount the Mercury+ XU8 SoC module the wrong way round on the base board - always check that the mounting holes on the base board are aligned with the mounting holes of the Mercury+ XU8 SoC module.

  • Page 17: Module Connector

    Symbol Value Size 54 mm Component height top 3.00 mm Component height bottom 1.35 mm Weight 34 g Table 3: Mechanical Data Module Connector Three Hirose FX10 168-pin 0.5 mm pitch headers with a total of 504 pins have to be integrated on the base board.

  • Page 18: User I/O

    User I/O 2.9.1 Pinout Information on the Mercury+ XU8 SoC module pinout can be found in the Enclustra Mercury Master Pinout [11], and in the additional document Enclustra Module Pin Connection Guidelines [10]. Warning! Please note that the pin types on the schematics symbol of the module connector and in the Master Pinout document are for reference only.

  • Page 19: I/O Pin Exceptions

    The I/O pin exceptions are pins with special functions or restrictions (for example, when used in combination with certain Mercury boards they may have a specific role). PCIe Reset Signal (PERST#) Table 6 lists the I/O pin exceptions on the Mercury+ XU8 SoC module related to the PCIe reset connection. I/O Name Module Connector Pin...

  • Page 20: Differential I/Os

    MIO30/42 does not apply in this case). I/O Pins with Level Shifter There are four signals on the Mercury+ XU8 SoC module that are routed from the FPGA banks to the module connector via level shifters - these are presented in Table 7.

  • Page 21: I/O Banks

    2.9.4 I/O Banks Table 8 describes the main attributes of the Programmable Logic (PL) and Processing System (PS) I/O banks, and indicates which peripherals are connected to each I/O bank. All I/O pins within a particular I/O bank must use the same I/O (VCC_IO) and reference (VREF) voltages. Bank Connectivity VCC_IO...

  • Page 22: Vcc_Io Usage

    C are used on other Enclustra modules; for compatibility purposes it is acceptable to power these pins even if they are not used on the Mercury+ XU8 SoC module. The Mercury+ XU8 SoC module may be used in combination with base boards having only two module connectors.

  • Page 23: Signal Terminations

    GPIOs; the suggested functions below are for reference only - always verify your MIO pinout with the Xilinx device handbook. Table 10 gives an overview over the MIO pin connections on the Mercury+ XU8 SoC module. Only the pins marked with “user functionality” are available on the module connector.

  • Page 24: Analog Inputs

    MIO Group Function Connection QSPI flash QSPI flash QSPI feedback clock Unused 10-11 On-board I2C bus and module connector via level shifter I2C interrupt On-board I2C bus 13-22 eMMC flash eMMC flash USB PHY 1 reset USB 2.0 PHY 1 24-25 LED0#, LED1# On-board LEDs...

  • Page 25: Multi-Gigabit Transceiver (Mgt)

    (connected to the PL) and GTR transceivers (connected to the PS). GTH Transceivers There are 16 GTH MGTs available on the Mercury+ XU8 SoC module organized in four FPGA banks - Table 12 describes the connections. The GTH banks are numbered differently depending on the MPSoC device equipped on the module:...

  • Page 26: Mgt Pairs

    GTR Transceivers There are four GTR MGT pairs and two reference input clock differential pairs on the Mercury+ XU8 SoC module connected to I/O bank 505; these are routed to module connector B. The naming convention for the GTR MGT I/Os is: MGTPS_<FUNCTION>_<PACKAGE_PIN>_<POLARITY>.

  • Page 27: Power

    Power Generation Overview The Mercury+ XU8 SoC module uses a 5 - 15 V DC power input for generating the on-board supply voltages (0.72/0.85/0.9 V, 0.85/0.9 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Some of these voltages (1.8 V, 2.5 V, 3.3 V) are accessible on the module connector.

  • Page 28: Generated Power Supplies

    -3E MPSoC device is equipped, an assembly option is available to switch the PS core operating voltage to 0.9 V. Please refer to the Enclustra Module Pin Connection Guidelines for general rules on the power pins [10]. The power consumption of the video codec unit (VCU) on the VCC_INT_VCU rail is limited to 4 A. This issue will be fixed starting with revision 3.

  • Page 29: Power Enable/Power Good

    Power Enable/Power Good The Mercury+ XU8 SoC module provides a power enable input on the module connector. This input may be used to shut down the DC/DC converters and LDOs for 0.72/0.85/0.9 V, 0.85/0.9 V, 0.9 V, 1.2 V, 1.8 V and 2.5 V.

  • Page 30: Voltage Supply Inputs

    In this case, VCC_IO needs to be switched off in the manner indicated in Figure 10. 2.11.3 Voltage Supply Inputs Table 16 describes the power supply inputs on the Mercury+ XU8 SoC module. The VCC voltages used as supplies for the I/O banks are described in Section 2.9.5. Pin Name Module Connector Pins...

  • Page 31: Power Consumption

    For Mercury modules an Enclustra heat sink kit is available for purchase along with the product. It repre- sents an optimal solution to cool the Mercury+ XU8 SoC module - the heat sink body is low profile and usually covers the whole module surface. The kit comes with a gap pad for the MPSoC device, a fan and required mounting material to attach the heat sink to the module PCB and baseboard PCB.

  • Page 32: Voltage Monitoring

    Clock Generation A 33.33 MHz oscillator is used for the Mercury+ XU8 SoC module clock generation; the 33.33 MHz clock is fed to the PS. A 100 MHz LVDS oscillator is connected to FPGA bank 65 and can serve as a reference for the PLL used to generate the clocks required for the PL DDR interface.

  • Page 33: Reset

    Pulling PS_POR# low resets the MPSoC device, the Ethernet and the USB PHYs, and the QSPI and eMMC flash devices. Please refer to the Enclustra Module Pin Connection Guidelines [10] for general rules regarding the connection of reset pins.

  • Page 34: Leds

    2.14 LEDs There are three active-low user LEDs on the Mercury+ XU8 SoC module - two of them are connected to the PS and one connected to the PL. Signal Signal Remarks Name Location PS_LED0# A18 (MIO24) User function/active-low PS_LED1#...

  • Page 35: Signal Description

    Please check the user manual regularly for updates. Any parts with different speed bins or temperature ranges that fulfill the requirements for the module variant may be used. 2.15.2 Signal Description Please refer to the Mercury+ XU8 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR4 SDRAM connections. 2.15.3 Termination Warning! No external termination is implemented for the data signals on the Mercury+ XU8 SoC module.

  • Page 36: Ddr4 Sdram (Pl)

    The DDR4 SDRAM memory controller on the MPSoC device supports speeds up to 2666 Mbit/s (1333 MHz), however the memories equipped on the Mercury+ XU8 SoC module are rated 2400 Mbit/s (1200 MHz). The maximum PL memory bandwidth on the Mercury+ XU8 SoC module is:...

  • Page 37: Ddr4 Sdram Type

    Please check the user manual regularly for updates. Any parts with different speed bins or temperature ranges that fulfill the requirements for the module variant may be used. 2.16.2 Signal Description Please refer to the Mercury+ XU8 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR4 SDRAM connections. 2.16.3 Termination Warning! No external termination is implemented for the data signals on the Mercury+ XU8 SoC module.

  • Page 38: Qspi Flash

    Table 28 describes the memory availability and configuration on the Mercury+ XU8 SoC module. As there is one QSPI flash chip equipped on the Mercury+ XU8 SoC module, type “single” must be selected when programming the flash from Vivado tools.

  • Page 39: Configuration

    Table 29: eMMC Flash Type Warning! Other flash memory devices may be equipped in future revisions of the Mercury+ XU8 SoC module. Please check the user manual regularly for updates. Any parts with different speeds and temperature ranges that fulfill the requirements for the module variant may be used.

  • Page 40: Signal Description

    VCC_CFG_MIO must be set to 1.8 V. Please note that this boot mode has not been tested, but it may be supported in the future. 2.20 Dual Gigabit Ethernet Two 10/100/1000 Mbit Ethernet PHYs are available on the Mercury+ XU8 SoC module, both connected to the PS via RGMII interfaces. 2.20.1 Ethernet PHY Type Table 30 describes the equipped Ethernet PHY devices type on the Mercury+ XU8 SoC module.

  • Page 41: External Connectivity

    Ethernet PHYs is connected to the I2C interrupt line, available on MIO pin 12. 2.20.3 External Connectivity The Ethernet signal lines can be connected directly to the magnetics. Please refer to the Enclustra Module Pin Connection Guidelines [10] for details regarding the connection of Ethernet signals. 2.20.4...

  • Page 42: Rgmii Delays Configuration

    USB 2.0 Two USB 2.0 PHYs are available on the Mercury+ XU8 SoC module, both connected to the PS to I/O bank 502. USB PHY 0 can be configured as host or device and USB PHY 1 can be used only as host.

  • Page 43: Signal Description

    PHY Type Manufacturer Type USB3320C Microchip USB 2.0 PHY Table 34: USB 2.0 PHY Type 2.21.2 Signal Description The ULPI interface for the PHY 0 is connected to MIO pins 52-63 for use with the integrated USB controller. The ULPI interface for the PHY 1 is connected to MIO pins 64-75. The MIO signals are shared between Ethernet PHY 1 and USB PHY 1, therefore only one of them can be used.

  • Page 44: Display Port

    (PMU) - more information on the PMU is available in the Zynq UltraScale+ MPSoC Technical Reference Manual [18]. The RTC crystal pad input and crystal pad output are connected on the Mercury+ XU8 SoC module to a 32.768 kHz oscillator.

  • Page 45: Device Configuration

    3 Device Configuration Configuration Signals The PS of the MPSoC needs to be configured before the FPGA logic can be used. Xilinx Zynq devices need special boot images to boot from QSPI flash, eMMC flash or SD card. For more information, please refer to the Zynq UltraScale+ MPSoC Technical Reference Manual [18].

  • Page 46: Module Connector C Detection

    VCC_IO pins on connector C are not used, C_PRSNT# does not influence the behavior of the module. For compatibility with other Enclustra modules, it is recommended to connect C_PRSNT# to GND on the base board if the designed base board has three connectors.

  • Page 47: Power-On Reset Delay Override

    The boot mode can be selected via two signals available on the module connector. Table 37 describes the available boot modes on the Mercury+ XU8 SoC module. Starting with revision 2, JTAG boot mode has been introduced to increase the usability with Xilinx tools, which may report issues when programming the on-board QSPI flash or when loading the FPGA bitstream in a non-JTAG boot mode.

  • Page 48: Jtag

    BOOT BOOT Mode Description Remarks MODE1 MODE0 Straps [3:0] 0110 Boot from eMMC flash 1110 Boot from SD card (with an ex- Not supported (may be sup- ternal SD 3.0 compliant level ported in the future) shifter; only available when VCC_CFG_MIO is 1.8 V) 0010 Boot from QSPI flash...

  • Page 49: External Connectivity

    The VREF pin of the programmer must be connected to VCC_CFG_MIO. It is recommended to add 22 series termination resistors between the module and the JTAG header, close to the source. Please refer to the Enclustra Module Pin Connection Guidelines for details on JTAG interface. 3.6.3 JTAG Boot Mode Starting with revision 2, support for JTAG boot mode has been added to increase the usability of the module with Xilinx tools, for example for QSPI flash programming or FPGA bitstream loading.

  • Page 50: Emmc Boot Mode

    In the SD card boot mode the PS boots from the SD card located on the base board. There are two SD card boot modes available on the Mercury+ XU8 SoC module. Please note that the SD boot mode with level shifter is currently not supported.

  • Page 51: Qspi Flash Programming From An External Spi Master

    3.13 Enclustra Module Configuration Tool In combination with an Enclustra base board, the QSPI flash can be programmed using Enclustra Module Configuration Tool (MCT) [16]. For this method, a non-QSPI boot mode must be used during QSPI flash programming. The entire procedure is described in the reference design documentation.

  • Page 52: I2C Communication

    4 I2C Communication Overview The I2C bus on the Mercury+ XU8 SoC module is connected to the MPSoC device and to the EEPROM, and is available on the module and debug connectors. This allows external devices to read the module type and to connect more devices to the I2C bus.

  • Page 53: Secure Eeprom

    An example demonstrating how to read the module information from the EEPROM memory is included in the Mercury+ XU8 SoC module reference design. Warning! The secure EEPROM is for Enclustra use only. Any attempt to write data to the secure EEPROM causes the warranty to be rendered void. 4.4.1...

  • Page 54: Product Information

    Module Product Family Reserved Revision Product Information Mercury+ XU8 SoC module 0x0335 0x[XX] 0x[YY] 0x0335 [XX][YY] Table 43: Product Information Module Configuration Addr. Bits Comment Min. Value Max. Value Comment MPSoC type See MPSoC type table (Table 45) 0x08 MPSoC device speed grade...

  • Page 55: Module Temperature Range

    Value Module Temperature Range Commercial Extended Industrial Table 46: Module Temperature Range Ethernet MAC Address The Ethernet MAC address is stored using big-endian byte order (MSB on the lowest address). Each module is assigned two sequential MAC addresses; only the lower one is stored in the EEPROM. D-0000-454-001 55 / 61 Version 07, 16.02.2021...

  • Page 56: Operating Conditions

    5 Operating Conditions Absolute Maximum Ratings Table 47 indicates the absolute maximum ratings for Mercury+ XU8 SoC module. The values given are for reference only; for details please refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [20].

  • Page 57: Recommended Operating Conditions

    Recommended Operating Conditions Table 48 indicates the recommended operating conditions for Mercury+ XU8 SoC module. The values given are for reference only; for details please refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [20]. Symbol Description...

  • Page 58: Ordering And Support

    6 Ordering and Support Ordering Please use the Enclustra online request/order form for ordering or requesting information: http://www.enclustra.com/en/order/ Support Please follow the instructions on the Enclustra online support site: http://www.enclustra.com/en/support/ D-0000-454-001 58 / 61 Version 07, 16.02.2021...
  • Page 59 List of Figures Hardware Block Diagram ........Product Code Fields .
  • Page 60 MPSoC Configuration Pins ........45 Boot Modes .
  • Page 61 [1] Enclustra General Business Conditions http://www.enclustra.com/en/products/gbc/ [2] Mercury+ XU8 SoC Module Reference Design https://github.com/enclustra [3] Mercury+ XU8 SoC Module IO Net Length Excel Sheet Ask Enclustra for details [4] Mercury+ XU8 SoC Module FPGA Pinout Excel Sheet Ask Enclustra for details...

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