Jtag; Jtag On Module Connector; Jtag Interface - Enclustra Mercury SA1 SoC Module User Manual

BOOT_ BOOT_
MODE1 MODE0
0 0
0 1
1 0
1 1
Table 31: Boot Modes
Please note that the passive serial mode is not supported on the Mercury SA1 SoC module nor has it been
tested on Enclustra side.
3.3

JTAG

The FPGA and the HPS JTAG interfaces are connected into one single chain available on the module con-
nector. If required for a third-party ARM debugger, the HPS JTAG interface may be routed to an optional
JTAG connector (J1000) on the Mercury SA1 SoC module.
The SoC device and the QSPI flash can be configured via JTAG using Intel tools.
The Mercury SA1 SoC module is compatible with Intel FPGA download cable (Blaster) I and II. Terasic USB
Blaster is compatible with the module, provided that the VCC_CFG_HPS_B3A_B8A is in the 2.5 V - 3.3 V
voltage range.
When the VCC_CFG_HPS_B3A_B8A is set to 1.8 V, the JTAG interface is functional only if the JTAG clock fre-
quency is lowered. This is an intermittent timing issue that affects certain modules and which is planned to
be fixed in future revisions of the module.
By default, the JTAG clock frequency is set to 24 MHz; to lower the frequency (for example to 16 MHz), the
following command can be used in the SoCEDS console:
jtagconfig --setparam 1 JtagClock 16M
3.3.1

JTAG on Module Connector

Signal Name Module Connector Pin
JTAG_TCK A-123
JTAG_TMS A-119
JTAG_TDI A-117
JTAG_TDO A-121
Table 32: JTAG Interface
5
BSEL[0] depends on the VCC_CFG_HPS_B3A_B8A voltage: it is set to 0 for 1.8 V and 1 for 2.5-3.3 V
D-0000-402-002
EMMC_EN# HPS boot
0 from FPGA
0 eMMC
1 QSPI
1 SDIO
Resistor
4.7 k pull-down
4.7 k pull-up to VCC_CFG_HPS_B3A_B8A
4.7 k pull-up to VCC_CFG_HPS_B3A_B8A
-
FPGA MSEL[4:0]
boot
passive 10000
serial
from HPS 00010
from HPS 00010
from HPS 00010
37 / 49
CSEL[1:0] BSEL[2:0]
00 001
5
00 10X
5
00 11X
5
00 10X
Version 06, 16.02.2021