Ddr3L Sdram; Ddr3L Sdram Type; Signal Description; Termination - Enclustra Mercury SA1 SoC Module User Manual

2.15

DDR3L SDRAM

There is a single DDR3 SDRAM channel on the Mercury SA1 SoC module attached directly to the HPS side
and is available only as a shared resource to the FPGA side.
The DDR3L SDRAM is connected to HPS I/O banks 6A and 6B, and it is always operated at 1.35 V (low power
mode). Four 8-bit memory chips are used to build a 32-bit wide memory.
The maximum memory bandwidth on the Mercury SA1 SoC module is:
800 Mbit/sec 32 bit = 3200 MB/sec
2.15.1

DDR3L SDRAM Type

Table 19 describes the memory availability and configuration on the Mercury SA1 SoC module.
Module
ME-SA1-D10 (commercial)
ME-SA1-D10 (commercial)
ME-SA1-D10 (industrial)
ME-SA1-D10 (industrial)
ME-SA1-D10 (industrial)
Table 19: DDR3L SDRAM Types
Warning!
Other DDR3L memory devices may be equipped in future revisions of the Mercury SA1 SoC module.
Please check the user manual regularly for updates. Any parts with different speed bins or temperature
ranges that fulfill the requirements for the module variant may be used.
2.15.2

Signal Description

Please refer to the Mercury SA1 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the
DDR3L SDRAM connections.
2.15.3

Termination

Warning!
No external termination is implemented for the data signals on the Mercury SA1 SoC module. There-
fore, it is strongly recommended to enable the on-die termination (ODT) feature of the DDR3 SDRAM
device.
D-0000-402-002
SDRAM Type
MT41K256M8DA-125:K
NT5CC256M8IN-DI
NT5CC256M8FN-DII
NT5CC256M8IN-DII
MT41K256M8DA-125IT:K
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Density Configuration
2 Gbit 256 M 8 bit
2 Gbit 256 M 8 bit
2 Gbit 256 M 8 bit
2 Gbit 256 M 8 bit
2 Gbit 256 M 8 bit
Manufacturer
Micron
Nanya
Nanya
Nanya
Micron
Version 06, 16.02.2021