Reset; Leds; Module Clock Resources; Reset Resources - Enclustra Mercury SA1 SoC Module User Manual

Signal Name Frequency
CLK_HPS1 50 MHz
CLK_FPGA 50 MHz
CLK_HPS2 External clock
CLK_ETH 25 MHz
Table 16: Module Clock Resources
2.13

Reset

The cold reset signal (POR) and the HPS warm reset signal (RST) of the SoC device are available on the
module connector.
Pulling HPS_POR# low resets the SoC device and the QSPI flash. Further, the CONFIG# pin is pulled low to
re-trigger the FPGA configuration. Please refer to the Enclustra Module Pin Connection Guidelines [10] for
general rules regarding the connection of reset pins.
Pulling HPS_RST# low resets the SoC device. For details on the functions of the HPS_NPOR and HPS_NRST
signals refer to the Intel documentation.
Table 17 presents the available reset signals. Both signals, HPS_POR# and HPS_RST#, have on-board 4.7 k
pull-up resistors to VCC_CFG_HPS_B3A_B8A.
Signal Name
HPS_POR#
HPS_RST#
Table 17: Reset Resources
Please note that HPS_POR# is automatically asserted if PWR_GOOD is low.
2.14

LEDs

The four LEDs on the Mercury SA1 SoC module are connected to the FPGA logic and the HPS in parallel. As
the LEDs are active-low it is recommended to use the I/Os in open collector mode.
Signal Name HPS GPIO
LED0# 48
LED1# 49
LED2# 50
LED3# 51
Table 18: LEDs
D-0000-402-002
Destination
HPS_CLK1
IO_RX_T1P_CLK7P_8A (pin D12)
HPS_CLK2
Gigabit Ethernet PHY
Connector Pin
A-132
A-124
FPGA Pin Remarks
AH12 User function/active-low
AF18 User function/active-low
AG21 User function/active-low
AH21 User function/active-low
27 / 49
Remark
HPS clock 1
FPGA clock
HPS clock 2
-
FPGA Pin Type
HPS_NPOR
HPS_NRST
Description
Cold reset
Warm reset
Version 06, 16.02.2021