Hps Jtag Connector; External Connectivity; Passive Serial Configuration; Emmc Boot Mode - Enclustra Mercury SA1 SoC Module User Manual

3.3.2

HPS JTAG Connector

Figure 12 presents the pinout of the HPS JTAG connector. To enable the HPS JTAG port on J1000, JTAG_PRESENT#
(pin 9) must be pulled low. J1000 connector is not equipped in the standard configuration. If needed, a 10-
pin 1.27 mm pinheader (e.g. Sullins GRPB052VWQS-RC) can be mounted.
In order to enable the return clock path for the HPS JTAG debug connector, pins 4 and 7 of J1000 must be
connected together, by mounting the R1107 resistor as displayed in the Figure 12 (please note that this con-
nection is incorrectly made on revision 2 modules). On revision 1 modules the return clock path connection
is done by default (no resistor present on this signal line).
Figure 12: HPS JTAG Connector
3.3.3

External Connectivity

JTAG signals can be connected directly on the base board to a JTAG connector. No pull-up/pull-down re-
sistors are necessary. The VCC pin of the programmer must be connected to VCC_CFG_HPS_B3A_B8A.
It is recommended to add 22
to the source. Please refer to the Enclustra Module Pin Connection Guidelines for details on JTAG interface.
3.4

Passive Serial Configuration

In the passive serial configuration mode the FPGA bitstream is programmed from an external source into
the SPI port of the FPGA. The HPS is configured afterwards via HPS2FPGA bridge. For more information,
please refer to the Cyclone V datasheet [18].
3.5

eMMC Boot Mode

In the eMMC boot mode, the HPS boots from the eMMC flash located on the module and configures the
FPGA logic from the HPS. The HPS configuration and the FPGA bitstream need to be stored in a boot image.
For more information, please refer to the Cyclone V datasheet [18].
D-0000-402-002
series termination resistors between the module and the JTAG header, close
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