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Mercury+ XU1 SoC Module
Purpose
The purpose of this document is to present the characteristics of Mercury+ XU1 SoC module to the user,
and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU1 SoC
module.
Summary
This document first gives an overview of the Mercury+ XU1 SoC module followed by a detailed description
of its features and configuration options. In addition, references to other useful documents are included.
Product Information
Product
Document Information
Reference / Version / Date
Approval Information
Written by
Verified by
Approved by
User Manual
Code
ME‐XU1
Reference
D‐0000‐428‐001
Name
DIUN
GLAC
IJOS
Enclustra GmbH – Räffelstrasse 28 – CH‐8045 Zürich – Switzerland
Name
Mercury+ XU1 SoC Module
Version
16
Position
Design Engineer
Design Expert
Manager, BU‐SP
Phone +41 43 343 39 43 – www.enclustra.com
Date
04.10.2023
Date
04.05.2016
12.05.2016
04.10.2023
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Summary of Contents for Enclustra Mercury+ XU1
- Page 1 Mercury+ XU1 SoC Module User Manual Purpose The purpose of this document is to present the characteristics of Mercury+ XU1 SoC module to the user, and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU1 SoC module.
- Page 2 Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior written permission of Enclustra GmbH, Switzerland. Although Enclustra GmbH believes that the information included in this publication is correct as of the date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
- Page 3 Document History Version Date Author Comment 04.10.2023 MGOS Updated for revision 5.0 modules: added EN‐numbers for all ver‐ sions, corrected voltage supply input for VCC_BAT, improved termi‐ nology, content, and layout for better readability and consistency 29.08.2021 TKAU Updated for revision 4.2 modules: added information on discon‐ tinuation of support for power converter switching frequency syn‐...
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Page 4: Table Of Contents
1.3.2 Enclustra Build Environment ........ - Page 5 ..... . . 57 3.13 Enclustra Module Configuration Tool ....... . . 58...
- Page 6 Secure EEPROM ..........60 4.4.1 Memory Map .
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Page 7: Overview
The Enclustra Build Environment [17] is available for the Mercury+ XU1 SoC module. This build system allows the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the desired target and download all the required binaries, such as bitstream and FSBL ﴾First Stage Boot Loader﴿. -
Page 8: Safety Recommendations And Warnings
1.1.7 Electromagnetic Compatibility The Mercury+ XU1 SoC module is a Class A product ﴾as defined in IEC 61000‐3‐2 standard﴿ and is not intended for use in domestic environments. The product may cause electromagnetic interference, for which appropriate measures must be taken. -
Page 9: Deliverables
Enclustra Build Environment The Enclustra Build Environment ﴾EBE﴿ [17] enables the user to quickly set up and run Linux on any En‐ clustra SoC module or system board. It allows the user to choose the desired target, and download all the required binaries, such as bitstream and FSBL. -
Page 10: Petalinux Bsp
1.3.3 Petalinux BSP The Enclustra Petalinux BSPs enable the user to quickly set up a Petalinux project and to run Linux on the Enclustra SoC module or system board. The documentation [19] describes the build process in detail and allows a user without Petalinux knowl‐... -
Page 11: Module Description
2 Module Description Block Diagram Figure 1: Hardware Block Diagram Figure 2: Hardware Block Diagram ‐ G1 Variants D‐0000‐428‐001 11 / Version 16, 04.10.2023... -
Page 12: Module Configuration And Product Models
The main component of the Mercury+ XU1 SoC module is the Xilinx Zynq UltraScale+ MPSoC device. Most of its I/O pins are connected to the Mercury+ module connector, making up to 214 regular user I/Os available to the user. Further, up to twenty MGT pairs are available on the module connector, mak‐... -
Page 13: Product Model Fields
MGT connectivity. Figure 3: Product Model Fields For the first revision modules or early access modules, the product model may not respect entirely this naming convention. Contact Enclustra for more information. D‐0000‐428‐001 13 / Version 16, 04.10.2023... -
Page 14: Numbers And Product Models
EN‐Numbers and Product Models Every product is uniquely labeled, showing the EN‐number and serial number. An example is presented in Figure 4. EN-Number EN100000 SN123456 Serial Number Figure 4: Module Label The correspondence between EN‐number and product model for each revision is shown in Table 2. The known issues of the product and the changes between the revisions are described in the Mercury+ XU1 SoC Module Known Issues and Changes document [7]. - Page 15 EN‐Number Part Name Revision Number EN105139 ME‐XU1‐6EG‐1I‐D11E R4.2 EN105138 ME‐XU1‐6EG‐1I‐D11E‐G1 R4.2 EN105137 ME‐XU1‐6CG‐1E‐D11E R4.2 EN105136 ME‐XU1‐6CG‐1E‐D11E‐G1 R4.2 EN105134 ME‐XU1‐15EG‐2I‐D12E R4.2 EN105133 ME‐XU1‐15EG‐2I‐D12E‐G1 R4.2 EN105132 ME‐XU1‐15EG‐1E‐D12E‐G1 R4.2 EN102614 ME‐XU1‐6EG‐1I‐D11E‐G1 R4.1 EN102604 ME‐XU1‐15EG‐1E‐D12E‐G1 R4.1 EN102603 ME‐XU1‐9EG‐2I‐D12E‐G1 R4.1 EN102602 ME‐XU1‐9EG‐1E‐D11E‐G1 R4.1 EN102601 ME‐XU1‐6CG‐1E‐D11E R4.1 EN102600 ME‐XU1‐6CG‐1E‐D11E‐G1...
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Page 16: Numbers And Part Names
EN‐Number Part Name Revision Number EN101918 ME‐XU1‐6EG‐1I‐D11E R2.0 Table 2: EN‐Numbers and Part Names D‐0000‐428‐001 16 / Version 16, 04.10.2023... -
Page 17: Top And Bottom Views
Top and Bottom Views Depending on the hardware revision and configuration, the module may look slightly different than shown in this document. 2.4.1 Top View Figure 5: Module Top View 2.4.2 Bottom View Figure 6: Module Bottom View D‐0000‐428‐001 17 / Version 16, 04.10.2023... -
Page 18: Top And Bottom Assembly Drawings
Top and Bottom Assembly Drawings Depending on the hardware revision and configuration, the module may look slightly different than shown in this document. 2.5.1 Top Assembly Drawing Figure 7: Module Top Assembly Drawing 2.5.2 Bottom Assembly Drawing Figure 8: Module Bottom Assembly Drawing D‐0000‐428‐001 18 / Version 16, 04.10.2023... -
Page 19: Module Footprint And Mechanical Data
Enclustra offers Mercury and Mercury+ modules of various geometries having widths of 56, 64, 65, 72 or 74 mm and having different topologies for the mounting holes. If different module types shall be fixed on the base board by screws, additional mounting holes may be required to accommodate different modules. -
Page 20: Module Connector
Ensure that the mounting holes on the base board are aligned with the mounting holes of the Mercury+ XU1 SoC module. Table describes the mechanical characteristics of the Mercury+ XU1 SoC module. A 3D model ﴾PDF﴿ and a STEP 3D model are available [9], [10]. Parameter... -
Page 21: User I/O
2.8.1 Pinout Information on the Mercury+ XU1 SoC module pins can be found in the Enclustra Mercury Master Pinout [12], and in the additional document Enclustra Module Pin Connection Guidelines [11]. The pin types on the schematic of the module connector and in the Master Pinout document are for reference only. -
Page 22: I/O Pin Exceptions
Table 6: I/O Pin Exceptions ‐ PERST# When the Mercury+ XU1 SoC module is used in combination with a Mercury+ PE1 base board as a PCIe device, the low value of the PERST# signal coming from the PCIe edge connector on the module connec‐... - Page 23 MIO[30,42] does not apply in this case﴿. I/O Pins with Level Shifter There are four signals on the Mercury+ XU1 SoC module that are routed from the FPGA banks to the module connector via level shifters ‐ these are presented in Table 7.
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Page 24: Assembly Options For Mgt Tx/Rx Signals
Figure 11: Assembly Options for MGT TX/RX Signals Figure 12: Assembly Options for MGT REFCLK Signals Module Variant Default Assembly Variant “G1” Assembly Variant Compatibility ME‐XU1‐R1/R2 ME‐XU7/ME‐XU8 Signal Name MPSoC Pin Connectivity IO_B66_Y10_B128_REFCLK0_F25_P IO_B66_Y10 MGT_B128_REFCLK0_F25_P IO_B66_N11_B128_REFCLK0_F26_N IO_B66_N11 MGT_B128_REFCLK0_F26_N IO_B66_L5_AD14_U2_B128_TX0_G27_P IO_B66_L5_AD14_U2_P MGT_B128_TX0_G27_P IO_B66_L5_AD14_U3_B128_TX0_G28_N IO_B66_L5_AD14_U3_N... -
Page 25: Differential I/Os
The information regarding the length of the signal lines from the MPSoC device to the module connector is available in Mercury+ XU1 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the total length of the differential pairs on the base board if required by the application. -
Page 26: Vcc_Io Usage
VCC_IO_B[x], respectively VCC_CFG_MIO pins. All VCC_IO_B[x] or VCC_CFG_MIO pins of the same bank must be connected to the same voltage. For compatibility with other Enclustra Mercury modules, it is recommended to use a single I/O voltage per module connector. - Page 27 Table 10: VCC_IO Pins 4 5 6 If the Mercury+ XU1 SoC module is used in combination with a base board having only two module connectors, the VCC_IO_B64 pin that powers I/O bank 64 is connected to the on‐board generated 1.8 V supply voltage.
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Page 28: Signal Terminations
HD banks may optionally be equipped with 100 differential termination resistors on the module. The resistor identifiers for each differential input pair can be retrieved from the Mercury+ XU1 SoC Mod‐ ule User Schematics [6]. Single‐Ended Outputs There are no series termination resistors on the Mercury+ XU1 SoC module for single‐ended outputs. -
Page 29: Mio Pins Connections Overview
Table gives an overview over the MIO pin connections on the Mercury+ XU1 SoC module. Only the pins marked with “user functionality” are available on the module connector. MIO Pins Default Function Second Function Connection [0:5] QSPI flash Trace interface... -
Page 30: Analog Inputs
For optimal performance of high‐speed interfaces, for example, PCIe, use redrivers on the base board. The maximum data rate on the MGT lines on the Mercury+ XU1 SoC module depends on the routing path for these signals. When using MGTs at high performance rates, ensure adequate signal integrity over the full signal path. -
Page 31: Mgt Pairs
If required by your application, ensure that capacitors are mounted on the base board, close to the module pins. GTH Transceivers There are 12 GTH MGTs available on the Mercury+ XU1 SoC module organized in three FPGA banks ‐ Table describes the connections. -
Page 32: Power
2.10.1 Power Generation Overview The Mercury+ XU1 SoC module uses a 5 V to 15 V DC power input for generating the on‐board supply voltages. The power output pins of the module are accessible on the module connector. On revision 3, the Mercury+ XU1 SoC module underwent a major redesign of the power circuitry in order to support all MPSoC device speedgrades, increase performance, and support power converter synchro‐... -
Page 33: Generated Power Supplies
MPSoC device is assembled, an assembly option is available to switch the PS core operating voltage to 0.9 V. PS and PL operation at 0.9 V is not supported on modules revision 1 and 2. Refer to the Mercury+ XU1 SoC Module Known Issues and Changes document [7] for details. -
Page 34: Power Enable/Power Good
1.8 V and 2.5 V. The list of regulators that can be disabled via PWR_EN signal is provided in Section 2.10.1. The PWR_EN input is pulled to VCC_3V3 on the Mercury+ XU1 SoC module with a 10 k resistor. The PWR_GOOD signal is pulled to VCC_3V3 on the Mercury+ XU1 SoC module with a 10 k resistor. -
Page 35: Voltage Supply Inputs
Do not leave V_IO pins floating. 2.10.3 Voltage Supply Inputs Table describes the power supply inputs on the Mercury+ XU1 SoC module. The VCC voltages used as supplies for the I/O banks are described in Section 2.8.5. Supply Module Connector... -
Page 36: Power Consumption
For Mercury modules an Enclustra heat sink kit is available for purchase along with the product. It rep‐ resents an optimal solution to cool the Mercury+ XU1 SoC module ‐ the heat sink body is low profile and usually covers the whole module surface. The kit comes with a gap pad for the MPSoC device, a fan and required mounting material to attach the heat sink to the module PCB and baseboard PCB. -
Page 37: Voltage Monitoring
2.10.7 Voltage Monitoring Several pins on the module connector on the Mercury+ XU1 SoC module are marked as VMON. These are voltage monitoring outputs that are used in the production test for measuring some of the on‐board voltages. -
Page 38: Clock Generation
505. A 24 MHz clock and a 25 MHz clock are used for the USB PHYs and Ethernet PHYs respectively. The crystal pads for the MPSoC RTC are connected to a 32.768 kHz oscillator on the Mercury+ XU1 SoC module. -
Page 39: Leds
LEDs There are three active‐low user LEDs on the Mercury+ XU1 SoC module ‐ two of them are connected to the PS and one is connected to the PL. The PS LED signals are shared with the debug connector trace signals on modules revisions 1 and 2. -
Page 40: Ddr4 Sdram
2.14 DDR4 SDRAM There is a single DDR4 SDRAM channel on the Mercury+ XU1 SoC module attached directly to the PS side and is available only as a shared resource to the PL side. The DDR4 SDRAM is connected to PS I/O bank 504. The memory configuration on the Mercury+ XU1 SoC module supports ECC error detection and correction;... -
Page 41: Termination
2.14.3 Termination No external termination is implemented for the data signals on the Mercury+ XU1 SoC module. Enclus‐ tra strongly recommends enabling the on‐die termination ﴾ODT﴿ feature of the DDR4 SDRAM device. 2.14.4 Parameters Table shows the parameters of the PS DDR4 SDRAM to be set in the Vivado project such that it cor‐... -
Page 42: Qspi Flash
Table describes the memory availability and configuration on the Mercury+ XU1 SoC module. As there is one QSPI flash chip assembled on the Mercury+ XU1 SoC module, type “single” must be selected when programming the flash from Vivado tools. Flash Type... -
Page 43: Emmc Flash
16 GB Table 28: eMMC Flash Characteristics Different flash memory devices may be assembled in future revisions of the Mercury+ XU1 SoC module. Any flash memory with a different speed and temperature range fulfilling the requirements of the module variant may be used. -
Page 44: Signal Description
Ethernet PHYs is connected to the I2C interrupt line, available on MIO pin 12. 2.18.3 External Connectivity The Ethernet signal lines can be connected directly to the magnetics. Refer to the Enclustra Module Pin Connection Guidelines [11] for details regarding the connection of Ethernet signals. 2.18.4 MDIO Address The MDIO interface is shared between the two Gigabit Ethernet PHYs ‐... -
Page 45: Phy Configuration
RX and TX data, it is recommended to adjust the pad skew delays as specified in Table 32. These values have been successfully tested on Enclustra side. The delays can be adjusted by programming the RGMII pad skew registers of the Ethernet PHY. Refer to the PHY datasheet for details. -
Page 46: Usb 2.0
USB 2.0 Two USB 2.0 PHYs are available on the Mercury+ XU1 SoC module, both connected to the PS to I/O bank 502. USB PHY 0 can be configured as host or device and USB PHY 1 can be used only as host. -
Page 47: Display Port
﴾PMU﴿ ‐ more information on the PMU is available in the Zynq UltraScale+ MPSoC Technical Reference Manual [22]. The RTC crystal pad input and crystal pad output are connected on the Mercury+ XU1 SoC module to a 32.768 kHz oscillator. -
Page 48: Secure Eeprom
Atmel DS28CN01 ﴾custom assembly﴿ Maxim Table 34: EEPROM Characteristics An example demonstrating how to read data from the EEPROM is included in the Mercury+ XU1 SoC module reference design [2]. 2.24 Debug Connector The Mercury+ XU1 SoC module may optionally be equipped with a debug connector that allows the user to perform debug operations using JTAG or TRACE signals connected to the ARM DAP, to monitor and control FPGA configuration signals and to have access to the I2C bus and UART. - Page 49 Pin Number Signal Name Description EMMC_IO2_PJTAG_TMS PJTAG TMS I2C_INT#_PJTAG_TCK PJTAG TCK EMMC_IO0_JTAG_TDI PJTAG TDI EMMC_IO1_PJTAG_TDO PJTAG TDO PJTAG_EN# PJTAG enable ﴾enable PJTAG boot mode﴿ 5, 20, 31, 32, 33, 34 Ground VCC_3V3 VCC_CFG_MIO VCC_ 1V8 PS_SRST# PS system reset PS_PROG# Configuration block reset ﴾Refer to Zynq UltraScale+ MPSoC Technical Reference Manual [22]﴿...
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Page 50: Debug Connector Interface - Revision 1 And 2 Modules
MIO pins 0 to 9 must be assigned to TRACE controller in the PS settings of the Vivado project. Additionally, starting with revision 2 modules, the trace clock multiplexer must be assembled. Refer to the Mercury+ XU1 SoC Module User Schematics [6] for details. D‐0000‐428‐001 50 / Version 16, 04.10.2023... -
Page 51: Device Configuration
3 Device Configuration Configuration Signals The PS of the MPSoC needs to be configured before the FPGA logic can be used. Xilinx Zynq devices need special boot images to boot from QSPI flash, eMMC flash or SD card. For more information, refer to the Zynq UltraScale+ MPSoC Technical Reference Manual [22]. -
Page 52: Pull-Up During Configuration
Pull‐Up During Configuration The Pull‐Up During Configuration signal ﴾PUDC﴿ is pulled to GND on the module; as PUDC is an active‐ low signal, all FPGA I/Os will have the internal pull‐up resistors enabled during device configuration. If the application requires the pull‐up during configuration to be disabled, this can be achieved by re‐ moving R201 component and by mounting R228 ‐... -
Page 53: Boot Mode
Table describes the available boot modes on the Mercury+ XU1 SoC module. PJTAG_EN# signal is only available on the optional debug connector. It has a 10 k pull‐up resistor to VCC_CFG_MIO, therefore it may be left unconnected. -
Page 54: Jtag
The VREF pin of the programmer must be connected to VCC_CFG_MIO. It is recommended to add 22 series termination resistors between the module and the JTAG header, close to the source. Refer to the Enclustra Module Pin Connection Guidelines for details on JTAG interface. 3.6.3 PJTAG on Debug Connector The JTAG pins available on the debug connector are used by the ARM DAP for debugging the PS. -
Page 55: Jtag Boot Mode
Signal Name Pin on Debug Connector PS Pin Resistor I2C_INT#_PJTAG_TCK MIO[12] 51.7 k pull‐up to VCC_3V3 EMMC_IO2_PJTAG_TMS MIO[15] 47 k pull‐up to VCC_1V8 EMMC_IO0_PJTAG_TDI MIO[13] 47 k pull‐up to VCC_1V8 EMMC_IO1_PJTAG_TDO MIO[14] 47 k pull‐up to VCC_1V8 Table 40: JTAG Interface ‐ ARM DAP Access via PJTAG Signals (valid only for modules revision 1 and 2) In the standard configuration, PJTAG boot mode is not supported. -
Page 56: Emmc Boot Mode
In the SD card boot mode the PS boots from the SD card located on the base board. There are two SD card boot modes available on the Mercury+ XU1 SoC module. The SD boot mode with level shifter is currently not supported. -
Page 57: Qspi Flash Programming From An External Spi Master
refer to the Xilinx documentation [22] and support. Alternatively, the QSPI flash can be programmed in u‐boot or Linux by the SPI controller in the PS or from an SPI external master. 3.12 QSPI Flash Programming from an External SPI Master The signals of the QSPI flash are directly connected to the module connector for flash access, as shown in Table 42. -
Page 58: Enclustra Module Configuration Tool
3.13 Enclustra Module Configuration Tool In combination with an Enclustra base board, the QSPI flash can be programmed using Enclustra Module Configuration Tool ﴾MCT﴿ [20]. For this method, a non‐QSPI boot mode must be used during QSPI flash programming. The entire procedure is described in the reference design documentation, and is only available starting with revision 2 modules. -
Page 59: I2C Communication
4 I2C Communication Overview The I2C bus on the Mercury+ XU1 SoC module is connected to the MPSoC device and to the EEPROM, and is available on the module and debug connectors. This allows external devices to read the module type and to connect more devices to the I2C bus. -
Page 60: Secure Eeprom
Secure EEPROM The secure EEPROM is used to store the module serial number and configuration. An example demon‐ strating how to read the module information from the EEPROM memory is included in the Mercury+ XU1 SoC module reference design. Any attempt to write data to the secure EEPROM causes the warranty to be rendered void. - Page 61 Module Configuration Addr. Bits Description Min. Value Max. Value Comment [7:4] MPSoC type See MPSoC type table ﴾Table 48﴿ 0x08 [3:0] MPSoC device speed grade [7:6] Temperature range See temperature range table ﴾Table 49﴿ Power grade 0 ﴾Normal﴿ 1 ﴾Low power﴿ [4:3] Gigabit Ethernet port count 0x09...
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Page 62: Mpsoc Device Types
Value MPSoC Device Type XCZU9EG ES XCZU6EG XCZU9EG XCZU15EG XCZU6CG Table 48: MPSoC Device Types Table shows the available temperature ranges. Value Module Temperature Range Commercial Extended Industrial Table 49: Module Temperature Range Ethernet MAC Address The Ethernet MAC address is stored using big‐endian byte order ﴾MSB on the lowest address﴿. Each module is assigned two sequential MAC addresses;... -
Page 63: Operating Conditions
5 Operating Conditions Absolute Maximum Ratings Table indicates the absolute maximum ratings for Mercury+ XU1 SoC module. The values given are for reference only. For details, refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [24]. Parameter Description Min. -
Page 64: Recommended Operating Conditions
Recommended Operating Conditions Table indicates the recommended operating conditions for Mercury+ XU1 SoC module. The values given are for reference only. For details, refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [24]. Parameter Description Min. Max. -
Page 65: Ordering And Support
6 Ordering and Support Ordering Use the Enclustra online request/order form for ordering or requesting information: http://www.enclustra.com/en/order/ Support Follow the instructions on the Enclustra online support site: http://www.enclustra.com/en/support/ D‐0000‐428‐001 65 / Version 16, 04.10.2023... -
Page 66: List Of Figures
List of Figures Hardware Block Diagram ........11 Hardware Block Diagram ‐... - Page 67 Gigabit Ethernet PHYs Characteristics ....... . . 43 USB1/ETH1 Selection .
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Page 68: References
Ask Enclustra for details [4] Mercury+ XU1 SoC Module FPGA Pinout Excel Sheet Ask Enclustra for details [5] Mercury+ XU1 SoC Module FPGA Pinout Assembly Variants Excel Sheet Ask Enclustra for details [6] Mercury+ XU1 SoC Module User Schematics Ask Enclustra for details...
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