Konica Minolta bizhub C658 Service Manual page 1567

bizhub C658/C558/C458/C368/C308/C258
Error code
CFD28
CFD29
CFD2A
CFD2B
CFD2C
CFD2D
CFD2E
CFD2F
6.17.4 CFD3# (bizhub C658/C558/C458)
Error code
CFD30
CFD31
CFD32
CFD33
CFD34
CFD35
CFD36
CFD37
CFD38
CFD39
CFD3A
CFD3B
CFD3C
CFD3D
CFD3E
CFD3F
6.17.5 CFD4# (bizhub C658/C558/C458)
Error code
CFD40
CFD41
CFD42
CFD43
Unsupported Request exists in dual scan image processing board
(Asic2014) memory target access
Poisoned TLP exists in dual scan image processing board (Asic2014)
memory target access
Unsupported Request TLP exists in dual scan image processing board
(Asic2014) config target access
Poisoned TLP exists in dual scan image processing board (Asic2014)
config target access
A rising edge is detected of VD input to the dual scan image
processing board (Asic2014) CPS
A falling edge is detected of VD input to the dual scan image
processing board (Asic2014) CPS
A rising edge is detected of VD input to the dual scan image
processing board (Asic2014) DMA03
A falling edge is detected of VD input to the dual scan image
processing board (Asic2014) DMA03
A falling edge is detected of VSYNC input to the dual scan image
processing board (Asic2014) DMA03
The PP image processing control section register field is accessed
during soft reset active of the PP image processing control section of
the dual scan image processing board (Asic2014).
The input image processing control section register field is accessed
during soft reset active of the input image processing control section of
the dual scan image processing board (Asic2014).
The output image processing control section register field is accessed
during soft reset active of the output image processing control section
of the dual scan image processing board (Asic2014).
The UART register in the controller IO control section is accessed
during clock gating of the dual scan image processing board
(Asic2014) UART.
The UART00 register is accessed during clock gating of the dual scan
image processing board (Asic2014) UART.
The UART01 register is accessed during clock gating of the dual scan
image processing board (Asic2014) UART.
The UART02 register is accessed during clock gating of the dual scan
image processing board (Asic2014) UART.
The UART03 register is accessed during clock gating of the dual scan
image processing board (Asic2014) UART.
A rising edge is detected of VD input to the dual scan image
processing board (Asic2014) FieryIF
A falling edge is detected of VD input to the dual scan image
processing board (Asic2014) FieryIF
A rising edge is detected of VD input to the dual scan image
processing board (Asic2014) DMA23
A falling edge is detected of VD input to the dual scan image
processing board (Asic2014) DMA23
A falling edge is detected of VSYNC input to the dual scan image
processing board (Asic2014) DMA23
EmperorIP is accessed during dual scan image processing board
(Asic2014) soft reset active
Dual scan image processing board (Asic2014) Emepror-IP error
Dual scan image processing board (Asic2014) external bus error
Dual scan image processing board (Asic2014) JPEG, JPEG related
interruption during internal processing at DMA14
Dual scan image processing board (Asic2014) JPEG, JPEG related
interruption during internal processing at DMA15
Dual scan image processing board (Asic2014) JPEG, JPEG related
interruption with multiple statuses during internal processing at DMA14
Item
Item
Item
K-239
K TROUBLESHOOTING > 6. ABORT CODE
Component
Component
Dual scan image
processing board (DSIPB)
Component
• MFP board (MFPB)
• Dual scan image
processing board
(DSIPB)
Rank
Rank
C
Rank
C