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A
4
I/O
3
A[0..23]
IRQ0#
D[0..31]
IRQ1#
IRQ2#
ACK
FLAG[0..3]
WR#
FLAG[4..9]
RD#
MS0#
PWM_EVENT0
MS1#
PWM_EVENT1
MS2#
MS3#
HBR#
HBG#
CS#
REDY#
SBTS#
SW#
CPA#
BR1#
BR2#
2
DMAR1#
EXT_CLK
DMAG1#
DMAR2#
RESET#
DMAG2#
I/O
PWR/RST
EXT_CLK
DSP_CLK
PLD_CLK
PLD_CLK
RESET#
RST
RST
PWR/RST
1
A
B
DSP
IRQ0#
A[0..23]
IRQ1#
D[0..31]
IRQ2#
FLAG[0..3]
FLAG[0..3]
FLAG[4..9]
FLAG[4..9]
MFLAG
PWM_EVENT0
PROM_CS#
PWM_EVENT1
MS0#
MS1#
HBR#
MS2#
HBG#
MS3#
CS#
REDY#
SDA10
RAS#
SBTS#
CAS#
SW#
SDWE#
CPA#
DQM
SDCKE
SDCLK0
BR1#
BR2#
TFS0
DMAR1#
DT0A
DMAG1#
DT0B
DMAR2#
TXCLK0
DMAG2#
RFS0
DR0A
DR0B
RXCLK0
TFS1
DT1A
DT1B
TXCLK1
RFS1
DSP_CLK
DR1A
DR1B
RESET#
RXCLK1
CODEC_ON#
Proc. Main
www.BDTIC.com/ADI
B
C
UART-CPLD
A[0..5]
D[0..7]
ACK
WR#
RD#
PROM_CS*
MS1#
PLD_CLK
PLD_CLK
RST
RST
UART-CPLD
A[0..23]
D[0..31]
ACK
WR#
Mem
RD#
A[0..19]
D[0..31]
RD#
PROM_CS#
MS3#
SDA10
RAS#
CAS#
SDWE#
DQM
SDCKE
SDCLK0
Memory
C
D
EMAFE
D[0..15]
EMAFE_WR#
EMAFE_WR#
EMAFE_RD#
EMAFE_RD#
EMAFE_CS#
EMAFE_CS#
EMAFE_ADDR
EMAFE_ADDR
CODEC_RST#
IRQ0#
IRQ1#
MFLAG
TFS0
DT0A
DT0B
TXCLK0
RFS0
DR0A
DR0B
RXCLK0
TFS1
DT1A
DT1B
TXCLK1
RFS1
CHAIN_CLK
DR1A
CHAIN_IN
DR1B
CODEC_CS0
RXCLK1
CODEC_CS1
EMAFE
Ana log Devices, Inc.
One Tech nology Way.
Norwood, MA 02062
Designed by Paragon Innovations, Inc .
email: info@paragon -tx.com
Title
ADSP-21065L EZ- LAB
{Page Title}
Size
Documen t Number
B
65-000299- 02 (1125-01-001-0201)
Date
Wed nesday, November 18, 1998
Drawn By
Kris Stafford
Filename
{Filename}
D
E
4
Codec
CODEC_RST#
3
CHAIN_CLK
CHAIN_IN
CODEC_CS0
CODEC_CS1
DT1A
TXCLK1
RFS1
DR1A
RXCLK1
CODEC_ON#
Codec
2
1
Rev
2.0
Approved
Sheet
4
of
8
E
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