Analog Devices ADSP-21065L EZ-KIT Lite Manual page 70

variable cs : std_logic;
begin
rd := not rd_bar;
wr := not wr_bar;
cs := not cs_bar;
case present_state is
when IDLE => u_ack <= '1';
u_ack_v <= '0';
if ((cs = '1') AND ((rd OR wr) = '1')
AND (std_match(addr, "001-"))) then
-- Proceed only if next_state <= CS1;
-- addressed and rd/wr
else
next_state <= IDLE;
end if;
when CS1 => u_ack <= '1';
u_ack_v <= '0';
if ((cs = '1') AND ((rd OR wr) = '1')
AND (std_match(addr, "001-"))) then
-- Proceed only if next_state <= CS2;
--
else
next_state <= IDLE;
end if;
when CS2 => u_ack <= '0';
u_ack_v <= '1';
if (wr = '1') then
next_state <= WR1;
else
next_state <= CS3;
end if;
when WR1 => u_ack <= '0';
u_ack_v <= '1';
next_state <= WR2;
when WR2 =>u_ack <= '0';
u_ack_v <= '1';
next_state <= WR3;
when WR3 => u_ack <= '0';
u_ack_v <= '1';
next_state <= WR4;
when WR4 => u_ack <= '0';
u_ack_v <= '1';
next_state <= WR_D1;
when WR_D1 => u_ack <= '0';
u_ack_v <= '1';
next_state <= ENDW1;
www.BDTIC.com/ADI
-- Not needed; for clarity
addressed and rd/wr
-- Improper cycle
-- Signal extended cycle
-- Write cycle
-- Read cycle
-- Continue Write Cycle
-- Continue Write Cycle
-- Continue Write Cycle
-- Continue Write Cycle
-- Continue Write Cycle
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