Analog Devices ADSP-21065L EZ-KIT Lite Manual page 71

when ENDW1 => u_ack <= '0';
u_ack_v <= '1';
next_state <= ENDW2;
when ENDW2 => u_ack <= '0';
u_ack_v <= '1';
next_state <= ENDW3;
when ENDW3 => u_ack <= '0';
u_ack_v <= '1';
next_state <= ENDW4;
when ENDW4 => u_ack <= '1';
u_ack_v <= '1';
next_state <= IDLE;
when CS3 => u_ack <= '0';
u_ack_v <= '1';
next_state <= CS4;
when CS4 => u_ack <= '0';
u_ack_v <= '1';
next_state <= CS5;
when CS5 => u_ack <= '0';
u_ack_v <= '1';
next_state <= CS6;
when CS6 => u_ack <= '0';
u_ack_v <= '1';
next_state <= RD1;
when RD1 => u_ack <= '0';
u_ack_v <= '1';
next_state <= RD2;
when RD2 => u_ack <= '0';
u_ack_v <= '1';
next_state <= RD3;
when RD3 => u_ack <= '0';
u_ack_v <= '1';
next_state <= RD4;
when RD4 => u_ack <= '1';
u_ack_v <= '1';
next_state <= ENDR1;
when ENDR1 => u_ack <= '1';
u_ack_v <= '1';
next_state <= IDLE;
end case;
end process uart_state;
with next_state select
uart_ctrl_d <= "111" when IDLE,
"101" when CS1,
"101" when CS2,
"100" when WR1,
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-- Continue Write Cycle
-- Continue Write Cycle
-- Continue Write Cycle
-- End Write Cycle
-- Continue Read Cycle
-- Continue Read Cycle
-- Continue Read Cycle
-- Continue Read Cycle
-- Continue Read Cycle
-- Continue Read Cycle
-- Continue Read Cycle
-- Continue Read Cycle
-- End Read Cycle
--
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