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Listing A
CPLD File
-- ********************************************************************
-- ** Copyright(c) 1998 Analog Devices, Inc. All Rights Reserved
-- ********************************************************************
-- ** Revision History
-- ** ----------------
-- ** 05/26/98 Original
-- ** 05/27/98 inverted ack output to ack_bar
-- ** Allows addition of open collector buffer to be added
-- ** 05/29/98 Changed address of UART
-- ** 08/15/98 Locked pins to prevent changes on next rev.s
-- ** 09/22/98 Changed ACK functionality (driven only when
needed)
-- ** Added Codec reset functionality
-- ** 09/28/98 Changed functionality of Codec Reset (1usec low)
-- **
-- **
-- ********************************************************************
-- ** 21065L.VHD
-- ** ----------
-- **
VHDL code for the CPLD on the ASPL-21065L evaluation board
-- **
-- **
Addresses:
-- **
UART:
-- **
EMAFE_Address:
-- **
EMAFE_Data:
-- **
CODEC_RESET:
-- **
-- **
Note: The ACK line is only driven when needed.
-- **
When the codec reset is written, the codec_rst line
-- **
goes low for > 1usec.
-- **
-- ********************************************************************
library ieee;
use ieee.std_logic_1164.all;
use work.std_arith.all;
entity interface is port (
reset
clk
addr
wr_bar, rd_bar, cs_bar
www.BDTIC.com/ADI
A3 A2 A1 A0
0
0
1
-
0
0
0
0
0
0
0
1
0
1
0
0
: in std_logic;
-- asynchronous reset
: in std_logic;
-- Clock input
: in std_logic_vector(3 down to 0);
: in std_logic;
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