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A
D[0..15]
4
EMAFE_ADDR
3
CHAIN_CLK
CHAIN_IN
CODEC_CS0
CODEC_CS1
EMAFE_CS#
EMAFE_RD#
EMAFE_WR#
TXCLK0
RXCLK0
TFS0
2
RFS0
DT0A
SPORT0
DR0A
DR0B
DT0B
TXCLK1
RXCLK1
TFS1
SPORT1
DR1B
RFS1
DT1A
DT1B
DR1A
1
J6
EMAFE
A
B
U14
1
OE
11
CLK
2
19
D0
MA0
D1
Q1
D1
3
18
MA1
D2
Q2
D2
4
17
MA2
D3
Q3
5
16
D3
MA3
D4
Q4
6
15
D4
MA4
D5
Q5
D5
7
14
MA5
D6
Q6
D6
8
13
MA6
D7
Q7
9
12
D7
MA7
D8
Q8
+3.3Vcc
20
10
Vcc
GND
74LVT574
+3.3Vcc
R76
+3.3Vcc
+5Vcc
www.BDTIC.com/ADI
B
C
U12
EMAFE_CS#
48
1OE
1
1DIR
25
2OE
EMAFE_RD#
24
2DIR
47
2
D0
MD0
1A1
1B1
D1
46
3
MD1
1A2
1B2
D2
44
5
MD2
1A3
1B3
D3
43
6
MD3
1A4
1B4
41
8
D4
MD4
1A5
1B5
D5
40
9
MD5
1A6
1B6
D6
38
11
MD6
1A7
1B7
D7
37
12
MD7
1A8
1B8
D8
36
13
MD8
2A1
2B1
D9
35
14
MD9
2A2
2B2
D10
33
16
MD10
2A3
2B3
32
17
D11
MD11
2A4
2B4
30
19
D12
MD12
2A5
2B5
D13
29
20
MD13
2A6
2B6
D14
27
22
MD14
2A7
2B7
26
23
D15
MD15
2A8
2B8
+3.3Vcc
7
4
Vcc1
GND1
18
10
Vcc2
GND2
31
15
Vcc3
GND3
42
21
Vcc4
GND4
28
GND5
34
GND6
39
GND7
45
GND8
74LVTH16245A
U11F
U8F
13
12
13
12
IRQ1#
74LCX14
74F06
+5Vcc
+5Vcc
C
D
Bypass Caps for
U12
+3.3Vcc
C91
C92
C93
+3.3Vcc
Bypass Caps for
U14
C105
C106
The ADSP-21065L must be
programmed to use a Hold
Time Cycle on MS1
for
proper operation of this
circuit
+3.3Vcc
+5Vcc
Ana log Devices, Inc.
One Tech nology Way.
Norwood, MA 02062
Designed by Paragon Innovations, Inc .
email: info@paragon -tx.com
Title
ADSP-21065L EZ- LAB
EMA FE-CODEC
Size
Documen t Number
B
65-000299- 02 (1125-01-001-0201)
Date
Wed nesday, November 18, 1998
Drawn By
Kris Stafford
Filename
{Filename}
D
E
4
C94
3
2
1
Rev
2.0
Approved
Sheet
6
of
8
E
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