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1 OVERVIEW
1.2 Block Diagram
S1C17W12
DCLK
DSIO
DST2
System clock
Clock generator
(CLG)
IOSC
FOUT
oscillator
∗1
OSC1
OSC1
oscillator
OSC2
OSC3
OSC3
OSC4
oscillator
EXOSC
EXOSC
input circuit
System reset controller
(SRC)
Power-on reset
#RESET
(POR)
V
DD
V
SS
Power generator
V
D1
∗1
(PWG2)
V
D2
C
V1
C
V2
1-4
CPU core & debugger
(S1C17)
Interrupt request
16-bit internal bus
Interrupt signal
Interrupt
controller
(ITC)
I/O port
(PPORT)
Watchdog timer
(WDT2)
Real-time clock
(RTCA)
Supply voltage
detector
(SVD)
16-bit timer
(T16)
3 Ch.
16-bit PWM timer
(T16B)
2 Ch.
Figure 1.2.1 S1C17W12 Block Diagram
Seiko Epson Corporation
Multiplier/divider
Coprocessor bus
(COPRO2)
Internal RAM
32-bit RAM bus
2K bytes
Flash memory
Instruction bus
48K bytes
P00–06
P07
P10–11
P12
P13–17
P20–26
P30–31
∗1
P40–43
PD0–D1
PD2
∗1
PD3–D4
RTC1S
EXSVD
TOUT00–01
TOUT10–11
CAP00–01
CAP10–11
EXCL00–01
EXCL10–11
*1 These pins do not exist in the SQFN7-48PIN package.
S1C17W12/W13 TECHNICAL MANUAL
V
PP
UART
USIN0–1
(UART2)
USOUT0–1
2 Ch.
Synchronous
SDI0
serial interface
SDO0
(SPIA)
SPICLK0
1 Ch.
#SPISS0
I
C
2
SDA0
(I2C)
SCL0
1 Ch.
RFIN0
R/F converter
REF0
(RFC)
SENA0
1 Ch.
SENB0
V
C1–3
C
P1–2
COM0–3
LCD driver
SEG0–1
(LCD4A)
SEG2–19
SEG20–25
LFRO
Display RAM
26 bytes
Sound generator
BZOUT
(SNDA)
#BZOUT
IR remote
controller
REMO
(REMC2)
CLPLS
1 Ch.
(Rev. 1.2)
∗1
∗1
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