Instruction Queue Buffer - Renesas R8C/Tiny Series Software Manual

Chapter 6 Calculation Number of Cycles

6.1 Instruction Queue Buffer

The R8C/Tiny series have 4-stage (4-byte) instruction queue buffers. If the instruction queue buffer has a
free space when the CPU can use the bus, instruction codes are taken into the instruction queue buffer.
This is referred to as "prefetch". The CPU reads (fetches) these instruction codes from the instruction queue
buffer as it executes a program.
Explanation about the number of cycles in Chapter 4 assumes that all the necessary instruction codes are
placed in the instruction queue buffer, and that 8-bit data is read or written to the memory without software
wait. In the following cases, more cycles may be needed than the number of cycles shown in this manual:
• When not all of the instruction codes needed by the CPU are placed in the instruction queue buffer...
Instruction codes are read in until all of the instruction codes required for program execution are avail-
able. Furthermore, the number of read cycles increases in the following cases:
(1) The number of read cycles increases as many as the number of wait cycles incurred when reading
instruction codes from an area in which software wait exists.
• When reading or writing data to an area in which software wait exists...
The number of read or write cycles increases as many as the number of wait cycles incurred.
• When reading or writing 16-bit data from/to the SFR or the internal memory...
The memory is accessed twice to read or write one 16-bit data. Therefore, the number of read or write
cycles increases by one for each 16-bit data read or written.
Note that if prefetch and data access occur in the same timing, data access has priority. Also, if more than
three bytes of instruction codes exist in the instruction queue buffer, the CPU assumes there is no free
space in the instruction queue buffer and, therefore, does not prefetch instruction code.
Figures 6.1.1 shows an example when starting a read instruction (without software wait).
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6.1 Instruction Queue Buffer