Ilvl2 To Ilvl0 Bis, Ipl - Renesas R8C/Tiny Series Software Manual

Chapter 5 Interrupt

5.2.3 ILVL2 to ILVL0 bis, IPL

Interrupt priority levels can be set by the ILVL2 to ILVL0 bits.
Table 5.2.1 shows how interrupt priority levels are set. Table 5.2.2 shows interrupt enable levels in
relation to IPL.
The following lists the conditions under which an interrupt request is acknowledged:
• I flag
• IR bit
• Interrupt priority level
The I flag, ILVL2 to ILVL0 bits, and IPL are independent of each other, so they do not affect any other bit.
Table 5.2.1 Interrupt Priority Levels
Interrupt priority
ILVL2–ILVL0
Level 0(interrupt disabled)
000
2
Level 1
001
2
010
Level 2
2
011
Level 3
2
Level 4
100
2
Level 5
101
2
110 Level 6
2
Level 7
111
2
When the IPL or the interrupt priority level of some interrupt is changed, the altered level is reflected in
interrupt handling at the following timing:
• If the IPL is changed by an REIT instruction, the changed level takes
effect beginning with the instruction that is executed two clock periods after the last clock of the REIT
instruction.
• If the IPL is changed by a POPC, LDC, or LDIPL instruction, the
changed level takes effect beginning with the instruction that is executed three clock periods after the
last clock of the instruction used.
• If the interrupt priority level of a particular interrupt is changed by an instruction such as MOV, the
changed level takes effect beginning with the instruction that is executed two clock or three clock
periods after the last clock of the instruction used.
= 1
= 1
> IPL
Priority
level order
Low
High
Table 5.2.2 Interrupt priority levels enabled by IPL
IPL
000
2
001
2
010
2
011
2
100
2
101
2
110
2
111
2
250
5.2 Interrupt Control
Enabled interrupt priority
levels
Interrupt levels 1 and above are enabled.
Interrupt levels 2 and above are enabled.
Interrupt levels 3 and above are enabled.
Interrupt levels 4 and above are enabled.
Interrupt levels 5 and above are enabled.
Interrupt levels 6 and above are enabled.
Interrupt levels 7 and above are enabled.
All maskable interrupts are disabled.