Adv7321A Configuration Modes - Xilinx VIODC User Manual

Chapter 3: Component and S-Video Interfaces
Table 3-1: Configuration Modes for ADV7403 Video Decoder Chip (Continued)
Notes:
1. The ADC sw1 and sw2 are unique to the VIODC input configuration.
Refer to the ADV7403 data sheet for other video configurations.

ADV7321A Configuration Modes

Table
Encoder device for each of the supported video standards.
The ADV7301 is mapped to I2C address 0x54/0x55.
Table 3-2: Configuration Modes for ADV7321A Video Encoder Chip
525P
www.BDTIC.com/XILINX
30
Register Register
Name Address
TLLC 0x3c
control
0x6b
0x85
0x86
0xb3
ADC sw1 0xc3
ADC sw2 0xc4
0x0e
0x52
0x54
0x0e
3-2, details the parameters setting for the internal registers of the ADV7321A Video
Register Register
Name Address
Power Mode 0x00
www.xilinx.com
Register
Value
0x5d PLL qpump
0xC2 [3:0]cpop_sel(1=20-bit,2=30-bit)
0x18 Turn off SSPD as sync is on Y
0x0b ENABLE SDTI line count mode
0xfe SDTI
0x54 [7:4]=adc1
[3:0]=adc0
0x86 [7]=sw_en,
[6]=SOG
[3:0]=adc2
0x80 Startup sequence
0x46
0x00
0x00
Register
Value
0xFE [7]=DACA_composite
[6]=DACB_luma
[5]=DACC_chroma
[4]=DACD_Y
[3]=DACE_Pr
[2]=DACF_Pb on
[1]=pll_off(1=off)
[0]=sleep(1=sleep)
Video Input/Output Daughter Card
Description
Description
UG235 (v1.2.1) October 31, 2007
R