Xilinx VIODC User Manual page 52

Chapter 7: Image Sensor Camera Interface
MHz. Normally, the camera output serial data includes 8 data bits plus HSYNC and
VSYNC, plus a START and STOP bit. Optionally, the output can be configured to include
10-bit data, with HSYNC and VSYNC encoded into the video data. Refer to the Micron
MT9V022 data sheet for more details on configuration modes.
The timing relationship between the clock and data is not specified, nor is the maximum
cable rate. This requires the FPGA receiver to have the ability to adjust or skew the camera
clock phase to clock in valid camera data. This is shown in
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SER_DATA_OUT
MT9V022
SHFT_CLK_OUT
Figure 7-2: Camera Clock
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XCV2P4 FPGA
dly
Clock Delay
ug235_ch6_02_120805
Figure 7-1.
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
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