Xilinx VIODC User Manual page 39

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Table 4-3: Analog XGA60
Register Name
Active Interface
PLL Div MSB
PLL Div LSB
VCO/CPMP
Phase Adjust
Clamp Placement
Clamp Duration
HSOUT Pulse width
Table 4-4: Analog SXGA60
Register Name
Active Interface
PLL Div MSB
PLL Div LSB
VCO/CPMP
Phase Adjust
Clamp Placement
Clamp Duration
HSOUT Pulse width
Table 4-5: Analog UXGA60
Register Name
Active Interface
PLL Div MSB
PLL Div LSB
VCO/CPMP
Phase Adjust
Clamp Placement
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Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
Register Register
Address Value
0x12 0x81 Force selection of analog input
0x01 0x53 PLL divider value. XGA60 has 1344 cycles per HSYNC
period. 1344 -1 = 0x53F
0x02 0xF0
0x03 0xB4 VCORNGE = 01, CURRENT = 101
0x04 0x80 Default phase = T/2
0x05 0x40 64 cycles after HSYNC
0x06 0x40 64 cycles in duration
0x07 0x88 136 cycles in HSYNC
Register Register
Address Value
0x12 0x81 Force selection of analog input
0x01 0x69 PLL divider value. SXGA60 has 1688 cycles per HSYNC
period. 1688 -1 = 0x697
0x02 0x70
0x03 0xD0 VCORNGE = 10, CURRENT = 100
0x04 0x80 Default phase = T/2
0x05 0x64 100 cycles after HSYNC
0x06 0x64 100 cycles in duration
0x07 0x70 112 cycles in HSYNC
Register Register
Address Value
0x12 0x81 Force selection of analog input
0x01 0x86 PLL divider value. UXGA60 has 2160 cycles per HSYNC
period. 2160 -1 = 0x86F
0x02 0xF0
0x03 0xD4 VCORNGE = 10, CURRENT = 101
0x04 0x80 Default phase = T/2
0x05 0x78 120 cycles after HSYNC
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Bus Interface
Description
Description
Description
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