Table of Contents
Advertisement
Chapter 3: Component and S-Video Interfaces
Table 3-2: Configuration Modes for ADV7321A Video Encoder Chip (Continued)
720P
10801
Refer to the ADV7321A data sheet for other video configurations.
www.BDTIC.com/XILINX
32
Register
Register
Name
Address
HD Mode
0x15
Reg 6
Power Mode
0x00
Input Mode
0x01
Mode
0x02
HD Mode
0x10
Reg 1
HD Mode
0x11
Reg 2
HD Mode
0x13
Reg 4
HD Mode
0x15
Reg 6
Power Mode
0x00
Input Mode
0x01
Mode
0x02
HD Mode
0x10
Reg 1
HD Mode
0x11
Reg 2
HD Mode
0x13
Reg 4
HD Mode
0x15
Reg 6
www.xilinx.com
Register
Value
0x00
0xFE
0x20
0x30
0x20
0x01
0x24
0x00
0xFE
0x20
0x30
0x68
0x01
0x04
0x00
Video Input/Output Daughter Card
Description
UG235 (v1.2.1) October 31, 2007
R
Advertisement
Table of Contents
