Sdi Receiver - Xilinx VIODC User Manual

Chapter 6: SDI Interface
Table 6-1
configured for the three different SDI bit rates. In SD-SDI mode, the 54 MHz clock out of
the ICS664-02 is multiplied by two by a Digital Clock Manager (DCM) to produce the
108 MHz reference clock needed by the RocketIO transceiver in the SDI receiver.
Table 6-1: RocketIO Reference Clock Generation

SDI Receiver

Figure 6-1
the FPGA.
The serial bitstream enters the RocketIO receiver after passing through an SDI cable
equalizer. The RocketIO receiver must be give a reference clock of the appropriate
frequency depending on the bit rate being received. If the reference clock frequency
doesn't match the bit rate of the input bitstream the receiver will not lock to the bitstream.
If the demo is in Auto Rx mode, the automatic rate detection logic will sequence the
RocketIO receiver through the three different bit rates supported by the demo until the
receiver locks.
SDI In
Cable
Equalizer
108 MHz
DCM
hd_sd
74.25 MHz or
74.1758 MHz
ICS664-02
freq control
1. It is possible to use 108 MHz instead of 54 MHz for SD-SDI in the transmitter. However, because the ICS664-
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44
shows the various frequencies produced by the PLL502 and ICS664-02 when
VCXO
Bit Rate
Frequency
1.485 Gb/s 13.5 MHz
1.4835 Gb/s 13.5 MHz
270 Mb/s 54 MHz
is a block diagram of the SDI receiver. Shaded blocks in the figure are external to
SD-SDI
Data
Recovery
RXP
RXN
RocketIO
20
RXDATA
REFCLK2
REFCLKSEL
BUFG
REFCLK RXRECCLK
RXUSRCLK
RXUSRCLK2
From ML402
Demo Mode
DIP switches
Figure 6-1: SDI Receiver Block Diagram
02 cannot directly generate 108 MHz, a DCM would be required to generate the 108 MHz clock resulting in
more jitter on the output of the SDI transmitter due to higher jitter on the reference clock. The receiver section
requires 108 MHz and cannot get by with 54 MHz. However, jitter on the RocketIO reference clock is not as
important for the receiver.
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ICS664-02 Frequency
74.25 MHz
74.1758 MHz
54 MHz
27 MHz Clock Enable
10 10 SD-SDI
SD-SDI
Descrambler Framer
20 HD-SDI
HD-SDI
Framer
Descrambler
AutoRate
Detection
hd_sd
Control
freq control
Rx REFCLK Tx REFCLK
74.25 MHz 74.25 MHz
74.1758 MHz 74.1758 MHz
108 MHz 54 MHz
10 EDH 10 S
Checker
clk
hd_sd
10 Y
Y
10 C
C
CRC Check
ug235_ch5_01_111405
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
R
SD
Analog
Video
HD
Analog
Video