Xilinx VIODC User Manual page 29

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Table 3-1: Configuration Modes for ADV7403 Video Decoder Chip (Continued)
720P
1080I
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Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
Register Register
Name Address
Primary 0x05
Mode
Video 0x06
Standard
Enable 0x1D
XTAL
ADC Power 0x3a
and PLL
Bias Control 0x3b
TLLC 0x3c
Control
0x6b
0x85
0x86
0xb3
ADC sw1 0xc3
ADC sw2 0xc4
0x0e
0x52
0x54
0x0e
Primary 0x05
Mode
Video 0x06
Standard
Enable 0x1D
XTAL
ADC power 0x3a
and PLL
Bias Control 0x3b
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Component Video Input and Output
Register
Value
0x01
0x0a [2:0] =PRIM_MODE
0x47 [3:0]= VID_STD
0x20 latch clock
0x80 External Bias Enable'
0x5d PLL qpump
0xC2 [3:0]cpop_sel(1=20-bit,2=30-bit)
0x18 Turn off SSPD as sync is on Y
0x0b ENABLE SDTI line count mode
0xfe SDTI
0x54 [7:4]=adc1
[3:0]=adc0
0x86 [7]=sw_en,
[6]=SOG
[3:0]=adc2
0x80 Startup sequence
0x46
0x00
0x00
0x01
0x0c [2:0] =PRIM_MODE
0x47 [3:0]= VID_STD
0x21 Latch clock
0x80 External Bias Enable'
Description
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