Xilinx VIODC User Manual page 31

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Table 3-2: Configuration Modes for ADV7321A Video Encoder Chip (Continued)
525PS
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Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
Register Register
Name Address
Input Mode 0x01
Mode 0x02
HD Mode 0x10
Reg 1
HD Mode 0x11
Reg 2
HD Mode 0x13
Reg 4
HD Mode 0x15
Reg 6
Power Mode 0x00
Input Mode 0x01
Mode 0x02
HD Mode 0x10
Reg 1
HD Mode 0x11
Reg 2
HD Mode 0x13
Reg 4
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Component Video Input and Output
Register
Value
0x10 [6:4]=mode
(7=PS54 6=SDHD 5=SDHD 4=10-bit 3=20-
bit 2=hd, 1=ps, 0=sd,)
[3]=clock_dly
[2]=cb0,
[0]=BTA compatibility
0x30 [5]=yuv_output
[4]=rgb_out_sync
[3]=use_rgb_matrix
[2]=black bar'
0x00 [7]macro_vision
[6]blank_low
[5]=720/1080i,
[4]=625/525p
[3:2]=sync_mode(0=hvsync,1=EAVcodes2
=async), [1:0]=output_levels(
0x01 [3]=tp_Field_en
[2]=test_pattern_on
[0]=data_valid_en
0x04 [7]=dbuf
[6]=4:2:2/4:4:4
[5]=SSAF
[3]=sync_filter
[2]=10-bit
[0]=crcb
0x00 [7:6]filter
[5]gamma_en
[4]=gamma_a/b
[3]dac_swap
[2]syncPrPb
[1]=rgb_input
0xFE
0x20
0x30
0x00
0x01
0x04
Description
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