Xilinx VIODC User Manual page 47

R
Table 6-3: ADV7321B HD Mode Register 1 (0x10) Settings by Video Format
Table 6-4:
Table 6-5:
www.BDTIC.com/XILINX
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
HD Video Format
720p60
720p50
1080i30
1080i25
All others
ADV7321B Register Settings for NTSC
Register Name Address
Power mode 0x00
Mode select 0x01
SD mode 0 0x40
SD mode 1 0x42
SD mode 3 0x44
SD mode 6 0x48
SD timing 0 0x4A
SD Fsc 0 0x4C
SD Fsc 1 0x4D
SD Fsc 2 0x4E
SD Fsc 3 0x4F
ADV7321B Register Settings for PAL
Register
Address
Name
Power mode 0x00
Mode select 0x01
SD mode 0 0x40
SD mode 1 0x42
SD mode 3 0x44
SD mode 6 0x48
SD timing 0 0x4A
SD Fsc 0 0x4C
SD Fsc 1 0x4D
www.xilinx.com
PicoBlaze Controller for the ADV7321B Video Encoder
Register 0x10 Value
Not supported by ADV7321B
Value
0xFC Enable DACs
0x00 SD input only
0x10 Select NTSC format
0x40 SD pixel data valid
0x00 Colorbars off
0x10 10-bit input
0x08 SD timing mode 0 and blank disabled
0x16
0x7c
0xF0
0x21
Value
0xFC Enable DACs
0x00 SD input only
0x11 Select PAL B, D, G, H, I format
0x40 SD pixel data valid
0x00 Colorbars off
0x10 10-bit input
0x08 SD timing mode 0 and blank disabled
0xCB
0x8A
0x2C
0x34
0x6C
0x74
Description
Description
47