Viobus Signal Definitions - Xilinx VIODC User Manual

Chapter 2: VIODC to ML402 Card Interface

VIOBUS Signal Definitions

Table 2-1: VIOBUS Signal Definitions
Signal
VIO Data Bus (a moderate-speed single-ended bus)
vio_up[25:0]
vio_up_ena
vio_dn[25:0]
vio_dn_ena
Sport Serial Bus (used to configure registers in the VIODC FPGA)
vio_sport_up
vio_sport_dn
vio_sport_sync
vio_sport_clk
I2C Serial Bus (used to configure registers in the video devices)
vio_i2c_sda_up
vio_i2c_sda_dn
vio_i2c_scl_up
Miscellaneous
vio_reset
Clock
vio_up_clk_lvds_P,N
Refer to the VIOBUS pinout in
www.BDTIC.com/XILINX
20
Description
Data bus to the VIODC
Pixel enable for
vio_up[25:0]
Data bus from the VIODC
Pixel enable for
vio_up[25:0]
Sport write data (16-bit
data, 16-bit address)
Sport return data
Sport sync pulse
Sport clock
I2C write data
I2C return data
I2C clock signal
Active High reset to
VIODC
www.xilinx.com
nbits Type
26 LVCMOS25 100 MHz
1 LVCMOS25 100 Mhz
26 LVCMOS25 100 MHz
1 LVCMOS25 100 MHz
1 LVCMOS25 10 MHz
1 LVCMOS25 10 MHz
1 LVCMOS25 10 MHz
1 LVCMOS25 10 MHz
1 LVCMOS25 400 kHz
1 LVCMOS25 400 kHz
1 LVCMOS25 400 kHz
1 LVCMOS25 10 MHz
1 LVDS25 400 MHz
Appendix A, "Reference Information"
Target Source
XGI Pins
Speed FPGA
ML402 hdr1[20:2],
hdr2[2:32]
ML402 hdr1[22]
VIODC hdr1[42:24],
hdr2[64:34]
VIODC hdr1[44]
ML402 hdr1[54]
VIODC hdr1[52]
ML402 hdr1[50]
ML402 hdr1[48]
ML402 hdr1[60]
VIODC hdr1[58]
ML402 hdr1[56]
ML402 hdr1[46]
ML402 hdr1[64:62]]
for signal locations.
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
R