Xilinx VIODC User Manual page 46

Chapter 6: SDI Interface
The code running on the PicoBlaze processor also provides an interactive debugging
capability for viewing and changing the contents of the registers in the ADV7321B encoder.
A ChipScope™ Pro VIO module is instantiated in the design to provide the user interface
to this debugging capability.
With the demo design loaded in the Virtex-II Pro FPGA on the VIODC, the debugger can
be activated by starting ChipScope Pro and loading the adv_debugger.cpj ChipScope
project. This project opens a VIO console as shown in
To read a register in the ADV7321B video encoder, simply type the register number in hex
in the Register Address field and click on the Read Strobe button. The data read from the
register is displayed in the Read Data field.
To write a register, type the register number in hex in the Register Address field and the
data to be written in hex in the Write Data field then click on the Write Strobe button. The
debugger will always do a read of the register after it is written and display the updated
value in the Read Data field.
Table 6-2
10 varies depending on the video format and is listed separately in
Table 6-4
PAL mode.
Table 6-2: ADV7321B Register Settings for HD
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46
Figure 6-2:
lists the settings of the ADV7321B registers when running in HD mode. Register
lists the settings used when the running in SD NTSC mode and
Register Name Address
Power mode 0x00
Mode select 0x01
HD mode 2 0x11
HD mode 3 0x12
HD mode 4 0x13
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Click here to reset the ADV7321B register
Enter register number of ADV7321B register to
be read or written here. Value is in hex.
Enter data to be written to ADV7321B register
here. Data is in hex.
Click here to write data to ADV7321B register.
Data read from ADV7321B register is
displayed here in hex.
Click here to read data from ADV7321B register.
ADV7321B Debugger
Value
0xFC Enable DACs
0x20 HD input only
0x01 Pixel data valid bit set to 1
0x00 Set all delays to 0
0x44 Set for 4:2:2 sampling and 10-bit data input
Figure 6-2.
ug235_ch6_02_111405
Table 6-3.
Table 6-5
Description
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
R
for SD