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Lattice Semiconductor
Figure 25. Frequency Summary Dialog Box
4. Click OK.
PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.
ispClock5400D Evaluation Board
This section describes the features of the ispClock5400D Evaluation Board in detail. The features appear in alpha-
betical order.
DIP Switch
To simplify the use of the evaluation board an 8-position DIP switch (SW1) is provided for common adjustments.
The switch can be roughly divided into four sections: reference oscillator control, PLL control, output enables, and
VCCO control. Table lists the switches and their respective functions. Note that for switch sections 6, 7, and 8 only
one should be on at a time. The default setting with all the switches to the left (OFF) enables the on-board oscilla-
tor, selects that as the clock reference, and allows the PLL to lock to that frequency.
Table 1.
DIP Switch Functions
Input/Output Connections
The evaluation board incorporates tapered transitions from the SMA connectors to the matched 50-ohm microstrip
transmission lines. All of the output transmission lines are matched in length to the sense signals (REFA, REFB,
and FEEDBACK) to support accurate timing measurements both for bank-to-bank and input-to-output. The header
at J16 (Appendix A, Figure 41) provides access to the essential control and monitor pins of the ispClock5406D
such as REFA_EN, REFB_EN, USER0, USER3, REFB_VTT, VCCO, and FBK_VTT.
Off-Board Clock Connections
An off-board CMOS clock can be used by connecting to the REFB_P (J2) SMA connector (Appendix A, Figure 35).
When using a CMOS reference clock, the negative differential input must be biased to VCC/2. For REF_B this is
done by populating R5, R7, and C53.
To the Left
SW1 – Section
0=
0=
0=
LOCK-LED
Unused
2.5V
1.8V
1.5V
ispClock5400D Evaluation Board
To the Right
1
1=REFA_EN
2
1=REFB_EN
3
1=REF-SEL
4
N/C=USER0
5
Unused
6
3.3V
7
3.3V
8
3.3V
24
User's Guide
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