Operation In Dual Output Mode (10 Or 8 Bit Depth) - Basler L800k User Manual

2.5.5.2 Operation in Dual Output Mode (10 or 8 Bit Depth)

In dual 10 bit mode, L801
respectively. On each clock cycle, the camera transmits data for two pixels at 10 bit depth, a line
valid bit and a data valid bit. The assignment of the bits is shown in Table 2-4 on page 2-11.
The Camera Link pixel clock is used to time data sampling and transmission. As shown in Figures
2-6 and 2-7, the camera samples and transmits data on each rising edge of the pixel clock.
The line valid bit indicates that a valid line is being transmitted and the data valid bit indicates that
valid pixel data is being transmitted. Pixel data is only valid when the line valid and data valid bits
are both high.
Operation in dual 8 bit mode is similar to dual 10 bit mode except that the two least significant bits
are dropped and only 8 bits of data per pixel are transmitted.
The data sequence outlined below, along with Figures
is happening at the inputs to the Camera Link transmitter in the camera.
Note that the timing used for sampling the data at the Camera Link receiver in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock) and on others, it must be
sampled on the falling edge. Also, some devices are available that allow you to se-
lect either rising edge or falling edge sampling. Please consult the data sheet for the
receiver you are using for specific timing information.
Video Data Sequence
When the camera is not transmitting valid data, the line valid and data valid bits transmitted on
each cycle of the pixel clock will be low. Once the camera has completed line acquisition, it will
begin to send valid data:
• On the clock cycle where pixel data transmission begins, the line valid and data valid bits will
become high. Ten of the bits transmitted during this clock cycle will contain the data for pixel
number one and ten of the bits will contain data for pixel number two.
• On the second cycle of the pixel clock, the line valid and data valid bits will be high. Ten of the
bits transmitted during this clock cycle will contain the data for pixel number three and ten of
the bits will contain data for pixel number four.
• This pattern will continue until all of the pixel data for the line has been transmitted. (A total of
4080 cycles.
• After all of the pixels have been transmitted, the line valid and data valid bits will become low
indicating that valid pixel data is no longer being transmitted.
Figure 2-6 shows the data sequence when the camera is operating in edge-controlled or level-
controlled exposure mode and Figure
in programmable exposure mode.
____________________
1
The data sequence assumes that the camera is operating in 10 bit mode. If the camera is
operating in 8 bit mode, only 8 bits of data per pixel will be transmitted.
2
When the AOI and Counter Stamp features are used, the number of cycles could be more or less
than 4080. See Sections
BASLER L800
k
Draft
/ L802 / L803
k k
1
2
)
2-7
3.7 and 3.8 for more information.
cameras operate with a 20 / 40 / 60 MHz pixel clock
k
shows the data sequence when the camera is operating
Camera Interface
2-6 and 2-7, describes what
2-15