Agilent Technologies E5052A Programmer's Manual page 486

Status Reporting System
Status Register Structure
Table B-6 Status Bit Definitions of Questionable Current Status Event Register
Issuing the *CLS command will clear all of the bits from the questionable current status
event register.
Table B-7 Status Bit Definitions of Questionable Power Status Event Register
Issuing the *CLS command will clear all of the bits in the questionable power status event
register.
Table B-8 Status Bit Definitions of Questionable Phase Status Event Register
Issuing the *CLS command will clear all of the bits in the questionable phase status event
register.
486
Bit Name
Position
0 DC Control Current Overloaded
1 DC Power Current Overloaded
2-15 Not used
Bit Name
Position
0 RF Level Insufficient
1 RF Level Overloaded
2 Insufficient IF Level
3 IF Level Overloaded
4-15 Not used
Bit Name
Position
0 Phase Lock Loop Unlocked
1 PLL Frequency Out of Range
2 PLL Input Overflow
3 A/D Overflow
4-15 Not used
Description
Set to "1" when excessive DC control current is
loaded.
Set to "1" when excessive DC power current is
loaded.
Always 0.
Description
Set to "1" when an insufficient level of RF input is
applied.
Set to "1" when an excessive level of RF input is
applied.
Set to "1" when an insufficient level of RF input is
applied.
Set to "1" when an excessive level of IF input is
applied.
Always 0.
Description
Set to "1" when Phase Lock Loop is not locked.
Set to "1" when PLL frequency is out of E5052A's
measurement range.
Set to "1" when PLL input overflows.
Set to "1" when signal level aturates at A/D.
Always 0.
Appendix B