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Summary of Contents for ADLINK Technology cPCI-6765
- Page 1 Intel 440BX with Mobile CPU 6U Compact PCI CPU CARD User’s Guide Recycled Paper...
- Page 3 Trademarks cPCI-6765(A) is a registered trademark of ADLINK Technology Inc. Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective...
- Page 4 Getting service from ADLINK Customer Satisfaction is the most important priority for ADLINK Tech Inc. If you need any help or service, please contact us. ADLINK Technology Inc. Web Site http://www.adlinktech.com Sales & Service Service@adlinktech.com NuDAQ + USBDAQ + PXI nudaq@adlinktech.com...
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Page 5: Table Of Contents
IDE Hard Drive ................. 8 1.3.15 IEEE-1284 Parallel Port/Printer Interface ......9 1.3.16 Universal Serial Bus (USB)............ 9 1.3.17 Serial I/O..................9 1.3.18 Keyboard/Mouse Controller........... 9 Specifications ..................10 1.4.1 cPCI-6765(A) Specifications ..........10 1.4.2 cPCI-R6765 Specifications..........15 Peripheral Connectivity.................16 Table of Contents • i... - Page 6 Chapter 2 Jumpers and Connectors............17 cPCI-6765(A) Board Outline and Illustration........18 Configuration ..................19 2.2.1 SW1 (Reset)................19 2.2.2 S1, S2, S3 and S4 (Setting LAN1 and LAN2 for Front or Rear Access)................20 2.2.3 JP2, JP3, JP4 and JP5 (COM2 RS-232/422/485/485+ Selectable) on RTM...............21 PMC VIO Zero Ω...
- Page 7 Using the Watchdog in an Application.......50 Hardware Doctor Utility.................51 Intel Preboot Execution Environment (PXE)........51 Appendix A ......................52 CPCI-6765A System Mode Hot Swap..........52 CPCI-6765 Peripheral Mode Hot Swap..........52 A.2.1 Hot Swap Controller Hardware Interface......53 A.2.2 Insertion and Removal Process .........54 Appendix B ......................56 21555 Application Notes ..............56...
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Page 8: List Of Tables
List of Tables Table 1: Power consumption with above configuration ......14 Table 2: Peripheral Connectivity Table............16 Table 3: Switch Cross-Reference Table...........19 Table 4: LAN Access Configuration ............20 Table 5: Setting LAN for 2.16 backplane or RTM........20 Table 6: JP2, JP3, JP4 and JP5 Settings ..........21 Zero Ω... - Page 9 List of Figures Figure 1: Bock Diagram of cPCI-6765(A) ............4 Figure 2: Board Layout..................18 Figure 3: Mounting Location of stand-off on 2.5” HDD ........37 Figure 4: Watchdog Timer Architecture ............49 Figure 5: l_stat Signal Implementation ............53 Figure 6: 21555 Hot-Swap controller Insertion and Removal Process ...54 Figure 7: 21555 Bus Addressing..............57...
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Page 10: Outline Of User's Manual
Outline of User’s Manual This manual is intended to assist users with understanding and configuring the cPCI-6765(A) 6U CompactPCI SBC and Rear I/O Transition Modules. It is divided into 5 chapters. Chapter 1, “Introduction”, gives an overview of the product features, applications, and specifications. -
Page 11: Chapter 1 Introduction
Introduction The cPCI-6765(A) CPU Board with Mobile Intel Pentium III Processor - M is a single board computer designed to work as a modular component in a high-performance CompactPCI system. It utilizes the Mobile Intel Pentium III Processor - M to provide extremely high PCI performance and the latest in memory and I/O technology combined with low power requirements. -
Page 12: Unpacking Checklist
ADLINK. Check the following items are included in the package, if there is any missing items, contact your dealer: • The cPCI-6765(A) module (May be equipped with different speed or capacity of CPU, RAM, and HDD). • This User’s Manual •... -
Page 13: Features
1.2 Features • PICMG 2.0 CompactPCI Specification R3.0 Compliant. • PICMG 2.1 CompactPCI Hot Swap Specification R2.0 Compliant. • PICMG 2.16 CompactPCI Packet Switch Backplane Specification node slot compatible. • PICMG 2.9 CompactPCI System Management Specification R1.0 Compliant. • Design for low power BGA2 Pentium-III CPU running at FSB 100MHz. •... -
Page 14: Functional Block
Functional Block The following topics are an overview of the cPCI-6765(A) main features as shown in the functional block diagram below. Mobile CPU Low Power Host Bus 100MHZ Memory AGP BUS CHIPS 82443 BX 100MHZ SO-DIMM 66MHZ M69000 PCI Bus 33MHZ... -
Page 15: Compactpci Bus Interface
PCI peripheral cards without the need for an external bridgeboard. The PCI-to-PCI Bridge is only available with the cPCI-6765 version. Refer to Appendix B for full application details of this chip Special features of the Intel 21555 include:... -
Page 16: Supported Memory
ADLINK factory provides pre-mounting memory for OEM project. Please contact ADLINK sales representatives for available memory configurations. 1.3.5 Interrupts Two enhanced interrupt controllers provide the cPCI-6765(A) with a total of 15 interrupt inputs. Interrupt controller features include support for: • Level-triggered and edge-triggered inputs •... -
Page 17: Dma
1.3.6 DMA Two enhanced DMA controllers are provided on the cPCI-6765(A) for use by the onboard peripherals. The cPCI-6765(A)'s DMA controllers reside in the Intel 82371EB (PIIX4E) device. 1.3.7 Real-Time Clock The real-time clock performs timekeeping functions and includes 256 bytes of general purpose, battery-backed, CMOS RAM. -
Page 18: Pci Mezzanine Card (Pmc) Interface
1.3.10 PCI Mezzanine Card (PMC) Interface The cPCI-6765(A) provides a location for one on-board PMC device with front panel access. The PMC interface is on the PCI Bus with PMC VIO default factory setting tied to 5.0V by 0-ohm resistors R33 and R34. If R33 and R34 are removed, and R38 and R49 are installed with 0 -ohm resistors, the PMC VIO is 3.3V. -
Page 19: Ieee-1284 Parallel Port/Printer Interface
12Mb/s. There are in total two USB ports on the cPCI-6765(A) with one routed for front panel access and the other is available through a Rear Transition Module and is controlled by the Intel 82371EB (PIIX4E) device. -
Page 20: Specifications
Specifications 1.4.1 cPCI-6765(A) Specifications General CompactPCI Features: • PCI Rev.2.1 compliant • PICMG 2.0 CompactPCI Rev. 3.0 compliant. • PICMG 2.1 CompactPCI Hot-swap specification Rev.2.0 compliant • PICMG 2.16 CompactPCI Packet Switch Backplane Specification node slot compatible. • PICMG 2.9 CompactPCI System Management Specification R1.0 Compliant. - Page 21 CompactPCI interface: • cPCI-6765 is a peripheral board design, suitable in peripheral slots, operated as a peripheral card in distributed multi -processor architecture. • Intel 21555 non-transparent PCI-to-PCI bridge interface on J1. • 32-bit/33MHz PCI operation. • Supports both 5V and 3.3V signaling Host Memory: •...
- Page 22 System Management Interface: • Qlogic Zircon CP Baseboard Management Controller (BMC) with 14 Kbytes SRAM internally. • Monitor onboard voltages, temperatures. • Support external 16-bit Flash ROM with a size of up to 1Mbyte (protected boot block required). IDE Ports: •...
- Page 23 Watchdog Timer: • Programmable I/O port 3F0h and 3F1h to configure watchdog timer, programmable timer 1~255 seconds or 1~255 minutes • A LED indicator on front faceplate for watchdog timer status indication • Bundled easy-programming library for DOS, Windows 95, 98, NT Hardware Monitoring: •...
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Page 24: Table 1: Power Consumption With Above Configuration
Front Panel LEDs and switch: • Power status (green) • IDE activity indicator (red) • Ethernet port 1&2: 10/100Mb (amber), activity (Green) • Watchdog timer status or Auxiliary indicator (green) • Hot-swap status indicator (blue) • On-handle limit switch for soft power-off signal triggering •... -
Page 25: Cpci-R6765 Specifications
The cPCI-6765(A) is supplied with a heatsink allowing the processor to operate between 0º and approximately 55º C ambient with a minimum of 1 meter per second of external airflow. It is the users' responsibility to ensure that the cPCI-6765(A) is installed in a chassis capable of supplying adequate airflow. -
Page 26: Peripheral Connectivity
Peripheral Connectivity cPCI-6765(A) cPCI-R6765 Faceplate Faceplate Serial Port (COM1) Y (DB-9) Serial Port (COM2) Y (J5, DB-9) Parallel Port Y (J5, DB-25) PS2 Keyboard Y (J3, PS2) Y (PS2, Combo) PS2 Mouse Y (J3, PS2) Floppy Ultra DMA33 Primary Ultra DMA33 Secondary... -
Page 27: Chapter 2 Jumpers And Connectors
Jumpers and Connectors This chapter will familiarize the user with the cPCI-6765(A) before getting started, it will provide information about the board layout, connector definitions, jumper setup and setting the PMC VIO, This will includes the following information: • cPCI-6765(A) board outline and illustration •... -
Page 28: Cpci-6765(A) Board Outline And Illustration
Board Outline and Illustration Lock/release lever BATTERY COM1 COM1 EIDE DIMM 1 DIMM 2 PMC Slot Connectors Heatsink KB/MS KB/MS LAN1 LAN1 LAN2 LAN2 LEDS RESET Figure 2: Board Layout 18 • Jumpers and Connectors... -
Page 29: Configuration
JP2 ~ JP5 (cPCI-R6765) COM2 RS-232/422/485/485+ Selectable Table 3: Switch Cross-Reference Table 2.2.1 SW1 (Reset) SW1 is a push-button on the front panel of the cPCI-6765(A). Pressing SW1 issues a hard reset and will reset the system Jumpers and Connectors • 19... -
Page 30: S1, S2, S3 And S4 (Setting Lan1 And Lan2 For Front Or Rear Access)
2.2.2 S1, S2, S3 and S4 (Setting LAN1 and LAN2 for Front or Rear Access) For convenience with wiring, the cPCI-6765(A) allows for either front or rear LAN1 and LAN2 access. Note that although both LAN1 and LAN2 are available on the front and rear, the same LAN port (e.g. LAN1 front and LAN1 rear), cannot be access simultaneously, and are set by dipswitches S1, S2, S3 and S4. -
Page 31: Jp2, Jp3, Jp4 And Jp5 (Com2 Rs-232/422/485/485+ Selectable) On Rtm
Table 6: JP2, JP3, JP4 and JP5 Settings 2.2.4 PMC VIO Zero Ω Shorting Resistors The cPCI-6765(A) contains two pairs of zero Ω shorting resistors that allow the user to configure the PMC VIO voltage to either +5V or +3.3V. The PMC interface is on the PCI Bus with PMC VIO default factory setting tied to +5.0V by... -
Page 32: Clear Cmos
To erase the CMOS RAM data: Unplug the cPCI-6765(A). Short pins 1 and 2 of JP1. Then reinstall the jumper back to normal location. Plug cPCI-6765(A) back to the chassis. Turn the power on. 22 • Jumpers and Connectors... -
Page 33: Cpci-6765(A) Connector Pin Assignments
Connector Pin Assignments 2.3.1 VGA Connector (Front and RTM) Signal Name Signal Name Green Blue N.C. N.C. N.C. N.C. HSYNC VSYNC Table 9: VGA Connector Pin Assignment 2.3.2 Ethernet (RJ-45) Connector (Front and RTM) Signal Function Transmit Data (+) -
Page 34: Ps/2 Mouse/Keyboard Connector (Front)
2.3.3 PS/2 Mouse/Keyboard Connector (Front) Pin # Signal Function KBDATA Keyboard data MSDATA Mouse data Power KBCLK Keyboard clock MSCLK Mouse clock Table 12: PS/2 Keyboard Pin Assignment 2.3.4 USB Connectors (Front and RTM) Signal Name Pin # USB- USB+ Ground Table 13: USB Connector Pin Assignment 2.3.5 COM1 Serial Ports... -
Page 35: Com2 Serial Ports On Rtm (Rs-232/422/485/485+)
Pin header on RTM SIGNAL FUNCTION RDCDJ1 Data Carrier Detect RDSRJ1 Data Set Ready RRXD1 Receive Data RRTSJ1 Request to Send RTXD1 Transmit Data RCTSJ1 Clear to Send RDTRJ1 Data Terminal Ready RRIJ1 Ring Indicate Ground No Connect Table 15: COM1 Pin Header on RTM 2.3.6 COM2 Serial Ports on RTM (RS-232/422/485/485+) COM2 serial port on the cPCI-R6765 can be configured as RS232, RS422, RS485 or RS485+ by setting the appropriate jumpers , refer to section 2.2.4. -
Page 36: Parallel Port Connector (On Rtm)
2.3.7 Parallel Port Connector (on RTM) Signal Name Pin # Pin # Signal Name Line printer strobe AutoFeed PD0, parallel data 0 Error PD1, parallel data 1 Initialize PD2, parallel data 2 Select PD3, parallel data 3 Ground PD4, parallel data 4 Ground PD5, parallel data 5 Ground... -
Page 37: Primary/Secondary Ide Connector (On Rtm)
2.3.9 Primary/Secondary IDE Connector (on RTM) Signal Name Pin # Pin # Signal Name Reset IDE Ground Host data 7 Host data 8 Host data 6 Host data 9 Host data 5 Host data 10 Host data 4 Host data 11 Host data 3 Host data 12 Host data 2... -
Page 38: Secondary Ide Connector (Front)
2.3.10 Secondary IDE Connector (Front) Signal Signal BRSTDRVJ DDP7 DDP8 DDP6 DDP9 DDP5 DDP10 DDP4 DDP11 DDP3 DDP12 DDP2 DDP13 DDP1 DDP14 DDP0 DDP15 PDDREQ PDIOWJ PDIORJ PIORDY PCSEL PDDACKJ IRQ14 DAP1 DIAG DAP0 DAP2 CS1P CS3PJ IDEACTPJ Table 20: 44-pin Secondary IDE Connector 28 •... -
Page 39: Pmc Connectors
2.3.11 PMC Connectors PMC J11 Connector Signal Signal -12V INTA# INTB# INTC# BUSMODE1# INTD# RESERVED +3.3V CLOCK GNT# REQ# PMCVIO AD[31] AD[28] AD[27] AD[25] C/BEJ[3]# AD[22] AD[21] AD[19] PMCVIO AD[17] FRAME# IRDY# DEVSEL# LCOK# RESERVED RESERVED PMCVIO AD[15] AD[12] AD[11] AD[9] C/BEJ[0]# AD[6]... -
Page 40: Table 22: Pmc J12 Pin Definition
PMC J12 Connector Signal Signal +12V TRST# RESERVED RESERVED RESERVED RESERVED BUSEMODE2# +3.3V PCI RESET BUSMODE3# +3.3V BUSMODE4# AD[30] AD[29] AD[26] AD[24] +3.3V IDSEL (AD[31]) AD[23] +3.3V AD[20] AD18 AD16 C/BEJ[2]# RESERVED TRDY# +3.3V STOP# PERR# +3.3V SERR# C/BEJ[1]# AD[14] AD13 AD10 AD[8]... -
Page 41: Compactpci Connectors
2.3.12 CompactPCI Connectors CompactPCI J1: 32-bit PCI System/Peripheral REQ64# ENUM# +3.3V S1AD[1] V(I/O) S1AD[0] ACK64# +3.3V S1AD[4] S1AD[3] S1AD[2] S1AD[7] +3.3V S1AD[6] AD[5] +3.3V S1AD[9] S1AD[8] S1C/B3[0]# GND S1AD[12] V(I/O) S1AD[11] S1AD[10] GND +3.3V S1AD[15] S1AD[14] S1AD[13] GND S1SERR# +3.3V S1PAR S1C/BE[1]# GND +3.3V... -
Page 42: Table 24: Compactpci J2 Pin Definition
CompactPCI J2: 64-bit PCI System/Peripheral GND Reserved Reserved Reserved Reserved GND GND Reserved Reserved Reserved Reserved GND Reserved Reserved Reserved GND GND Reserved Reserved Reserved Reserved GND GND Reserved Reserved Reserved Reserved GND GND Reserved Reserved Reserved GND DEG# GND Reserved FAL# Reserved Reserved GND GND Reserved Reserved Reserved... -
Page 43: Table 25: Compactpci J3 Pin Definition
COMPACTPCI J3: LAN, COM, KEYBOARD&MOUSE, FDD, USB, LPa_DA+ LPa_DA - LPa_DC+ Lpa_DC- (TX+) (TX-) LPa_DB+ LPa_DB- LPa_DD+ Lpa_DD- (RX+) (RX-) LPb_DA+ LPb_DA - LPb_DC+ LPb_DC- (TX+) (TX-) LPb_DB+ LPb_DB- LPb_DD+ LPb_DD- (RX+) (RX-) PDACT# PDCS1# PDCS3# PDA0 PDA2 PPDIAG PDCS16# PDIRQ14 PDA1 PDDACK# GND... -
Page 44: Table 26: Compactpci J5 Pin Definition
COMPACTPCI J5: COM, Printer, USB, 2 22 GND RI2# DTR2# CTS2# TXD2 RTS2# 21 GND RXD2 DSR2# DCD2# (CLK6) 20 GND AUTOFD# ERRORP# GND (CLK5) 19 GND SLCTIN# PINIT# PSTROB# GND 18 GND PPD0 PPD1 PPD2 PPD3 17 GND SLCT PPD4 (REQ6#) (GNT6#) -
Page 45: Chapter 3 Getting Started
Getting Started This chapter gives a summary of what is required to setup an operational system using the cPCI-6765(A). Hardware installation and BIOS overview is discuss. CPU Installation The cPCI-6765(A) CPU module supports a low power Mobile Intel Pentium-III, with a front side bus (FSB) of 100 MHz. This product is shipped with a CPU and a CPU heatsink pre-mounted on the board. -
Page 46: Hdd And Cf Installation
Check to make sure the SO-DIMM is inserted securely. HDD and CF Installation The cPCI-6765(A) can be installed with a slim -type HDD mounting bracket where a 2.5 inches IDE drive can be seated. The HDD can be pre-installed when the equipment is shipped or optionally by the user. However, if users wish to install the HDD, the HDD mounting kit is requited. -
Page 47: Hdd Installation For Cpci-6765(A)
3.3.1 HDD Installation for cPCI-6765(A) Find the HDD accessory pack inside your original package. (Users purchasing the OEM model, non-standard, customized or special configuration model, the HDD accessory package may not be included as part of the packaging. Please contact ADLINK dealers or sales representatives to purchase this accessory pack). -
Page 48: Bios Configuration Overview
BIOS Configuration Overview This topic presents an introduction to the Award PnP BIOS Setup Utility. For more detailed information about the BIOS and other utilities, see the BIOS Manual. The BIOS has many separately configurable features. These features are selected by running the built-in Setup utility. System configuration settings are saved in a portion of the battery-backed RAM in the real-time clock device and are used by the BIOS to initialize the system at boot up or reset. -
Page 49: Operating System Installation
Operating System Installation For more detailed information about your operating system, refer to the documentation provided by the operating system vendor. Install peripheral devices. CompactPCI devices are automatically configured by the BIOS during the boot sequence. Most operating systems require initial installation on a hard drive from a floppy or CDROM drive. -
Page 50: Chapter 4 Driver Installation
Driver Installation To install the drivers for the cPCI-6765(A), refer to the installation information in this chapter. Basic information is presented in this section, however, for more detailed installation information for non-Windows Operating Systems, refer to the extensive explanation inside the ADLINK CD. The drivers are... -
Page 51: Vga Drivers Installation
VGA Drivers Installation This section provides information on how to install the VGA driver that come in the CD with the package. Please follow the instructions carefully in this section. Note that there must be relevant software installed in your system before you are permitted to install the VGA driver. -
Page 52: Display Driver For Windows 2000
You will then see a warning panel about Third Party Drivers, Click yes to finish the installation. Once the installation is completed, the system must be shut down and restarted for the new drivers to take effect. Note: After installing the VGA/AGP drivers, and you discover the driver does not work probably. -
Page 53: Installing Drivers For Windows Xp
4.1.4 Installing Drivers for Windows XP The following section describes the normal procedures for installing the display driver for Windows XP. Installing the Drivers for Windows XP Click the "Start" button, then select t h e "Settings" tab and click on “Control Panel". -
Page 54: Lan Driver Installation
LAN Driver Installation This section describes the LAN driver installation procedures for the onboard Ethernet controller Intel 82559. The Intel 82559 is a 32-bit 10/100MBps Ethernet controller for the PCI local bus-compliant PC. It supports the bus mastering architecture, and Auto-negotiation features which makes it possible to combine a common Ethernet cable (RJ-45 connector with twisted-pair cabling) for use with both 10Mbps and 100Mbps connection. -
Page 55: Intel 82559 Driver Installation On Windows 98
4.2.2 Intel 82559 Driver Installation on Windows 98 Windows 98 will attempt to install a standard LAN driver automatically. To guarantee compatibility, manually install the most updated LAN driver, which is stored in the ADLINK CD. After installing Windows 98, update to the most updated driver using the following procedures. -
Page 56: Intel 82559 Driver Installation On Windows 2000
4.2.3 INTEL 82559 Driver Installation on Windows 2000 Windows 2000 will attempt to install a standard LAN driver automatically. To guarantee compatibility, manually install the most updated LAN driver, which is stored in the ADLINK CD. After installing Windows 2000, update to the most updated driver using the following procedures Boot Windows 2000, Click Start. -
Page 57: Intel 82559 Driver Installation On Windows Xp
4.2.4 Intel 82559 Driver Installation on Windows XP Windows XP will attempt to install a standard LAN driver automatically. To guarantee compatibility, manually install the most updated LAN driver, which is stored in the ADLINK CD. After installing Windows XP, update to the most updated driver using the following procedures. -
Page 58: Intel 82559 Driver Installation On Windows Nt
4.2.5 Intel 82559 Driver Installation on Windows NT Before installing the LAN driver on Windows NT, copy the LAN driver files in the CD to a floppy diskette. Insert a new diskette into drive A: then type the following batch command under a DOS environment to copy the relative NT LAN drivers X:\CHIPDRV\LAN\100PDISK. -
Page 59: Chapter 5 Utilities
Watchdog Timer Overview The primary function of the watchdog timer is to monitor the cPCI-6765(A)’s operation and to reset the system if the software fails to function as programmed. The major features of the watchdog timer are: •... -
Page 60: Using The Watchdog In An Application
The cPCI-6765(A)’s custom watchdog timer circuit is implemented in a programmable logic device. The watchdog timer contains a "Control and Status Register". The register allows the BIOS or user applications to determine if a watchdog time out was the source of a particular reset. -
Page 61: Hardware Doctor Utility
Windows 98 or Windows NT. Intel Preboot Execution Environment (PXE) The cPCI-6765(A) series supports Intel Preboot Execution Environment (PXE), which provides the capability of boot-up or executing an OS installation through the Ethernet ports. There should be a DHCP server in the network with one or more servers running PXE and MTFTP services. -
Page 62: Cpci-6765A System Mode Hot Swap
CPCI-6765 Peripheral Mode Hot Swap The cPCI-6765 is designed with an INTEL 21555 hot-swap controller, which supports hot-swap event pin, p_enum_l. This signal is routed to the host CPU through the Compact PCI connector. This signal informs the CPU that the configuration of the system has changed;... -
Page 63: Hot Swap Controller Hardware Interface
A.2.1 Hot Swap Controller Hardware Interface The US1010 low dropout regulator generates the 1V pre-charge voltage for the data bus lines. The output of the US1010 is set to 1.8V, but the voltage is further dropped by the 1N4148 diode to generate the 1V. The pre-charge circuit is capable of sourcing and sinking 40mA. -
Page 64: Insertion And Removal Process
A.2.2 Insertion and Removal Process The flow chart below is the 21555 Hot-Swap controller insertion and removal process. Figure 6: 21555 Hot-Swap controller Insertion and Removal Process 54 • Appendix A... - Page 65 Ejector handle is closed (micro-switch opens, and l_stat is sampled low). The cPCI-6765 has now been completely seated and the local initialization is complete. It’s ready for host configuration and initialization. The 21555 sets the INS_STAT bit and asserts p_enum_l to the host. Upon detecting p_enum_l asserted the host processor initializes the card.
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Page 66: 21555 Application Notes
Appendix B 21555 Application Notes The cPCI-6765 incorporates an INTEL 21555 Non-transparent PCI-to-PCI Bridge to operate at peripheral mode. As a peripheral card, it is recognized as a device on the host bus as well as the local side. So an extra device driver is needed to make it work. -
Page 67: Operating Therory
Run-time Includes features such as Typically has only resources doorbell interrupts, I20 message configuration unit, and so on that must be registers; no device managed by the device driver. driver is required. Clocks Generates secondary bus clock Generates one or output. -
Page 68: Figure 8: Setup Register
Figure 8: Setup Register The translation base registers hold the addresses to be trans lated to. As mentioned above, if an address translation is triggered, the 21555 will look up the base register and calculate the target-translated address. Figure 8 illustrates the actions. -
Page 69: Programming Notes
Programming notes In this section, we will discuss the detailed programming techniques. Including sample codes. If needed, modify the source to fit the actual environment. Source codes are packed within the All-In-One CD-ROM. Search and Register device Map Bus Address to Virtual Address Create Memory Buffer for Other Side... -
Page 70: Sample Code
B.3.1 Sample Code Test platform: Linux kernel 2.4.18 for x86 CPU B.3.2 Search and Register device … dev=pci_find_subsys(VENDOR,DEVICE,SUBSYSTEM_VENDOR,SUBSYSTEM_ DEVICE,NULL); …. B.3.3 Map Bus Address to Virtual Address int deviceMapMem(Spull_Dev *pDE) ULONG memSize; ULONG PCIaddr; PVOID SYSaddr; //map BAR0(CSR) pDE->BAR0VirtualWindowAddress = 0; memSize = pDE->thisPhysicalMemorySize[BAR0];... - Page 71 PDEBUG("R2D2DeviceMapMem: calling hal translate\n"); SYSaddr = ioremap(PCIaddr,memSize); if (SYSaddr) pDE->BAR2VirtualWindowAddress = SYSaddr; pDE->cachedDisk = false; PDEBUG("R2D2DeviceMapMem: Remote DiskBuffer mapped in uncacheable memory @ %p\n",SYSaddr); else PWARN("R2D2DeviceMapMem: unable to map Remote DiskBuffer \n"); return 1; //map failed //map BAR3 pDE->BAR3VirtualWindowAddress = 0; memSize = pDE->thisPhysicalMemorySize[BAR3];...
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Page 72: Create Memory Buffer For Other Side
B.3.4 Create Memory Buffer for Other Side int allocatePools(Spull_Dev *pDE) ULONG address; int order = bytes_to_order(SPULL_SIZE*1024); int bytes; do { address = __get_free_pages(GFP_KERNEL, order); if (address != 0) /* Success */ bytes = PAGE_SIZE << order; memset((void *) address, 0, bytes); pDE->RemoteUserBufferSize=bytes;... -
Page 73: Syncing With Setting And Exchange Base Address
B.3.5 Syncing with Setting and Exchange Base address if (pDE->ThisInterface == PRIMARY_INTERFACE) writel(pDE->RemoteUserBufferLogicalAddr, DB_ADDR(pDE->BAR0VirtualWindowAddress,BAR_UP_BAR2_XLAT_BASE)); value = sync_wait; done = false; PDEBUG("R2D2FindInitDevice: Waiting for signal from Secondary Interface.BAR_UP_BAR2_XLAT_BASE set to %08lX\n",pDE->RemoteUserBufferLogicalAddr); while (value-- && (!done)) if ((pDE->LocalDiskLogicalAddr = readl(DB_ADDR(pDE->BAR0VirtualWindowAddress,BAR_DOWN_BAR2_XLAT_B ASE))) != 0) pDE->fullDuplex = true;... - Page 74 DB_ADDR(pDE->BAR0VirtualWindowAddress,BAR_DOWN_BAR2_XLAT_BASE)); value = sync_wait; done = false; PDEBUG("R2D2FindInitDevice: Waiting for signal from Primary Interface.BAR_DOWN_BAR2_XLAT_BASE set to %08lx\n",pDE->RemoteUserBufferLogicalAddr); while (value-- && (!done)) if ((pDE->LocalDiskLogicalAddr = readl(DB_ADDR(pDE->BAR0VirtualWindowAddress, BAR_UP_BAR2_XLAT_BASE))) != 0) pDE->fullDuplex = true; done=true; if (!pDE->fullDuplex) PWARN("R2D2FindInitDevice: Timed out Waiting for signal from Primary Interface.\n");...
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Page 75: Init Interrupt Register
B.3.5 Init Interrupt Register int initializeInterrupt(Spull_Dev *pDE) int result; PDEBUG("initInterrupt: Entered Interrupt Initialization routine.\n"); if (pDE->IRQLine) PDEBUG("InitInterrupt:21555 irqline %d\n",pDE->IRQLine); disableDbInterrupt(pDE,pDE->ThisInterface,0xFFFF); PDEBUG("InitInterrupt: 21555 interrupt disabled\n"); enableDbInterrupt(pDE,pDE->ThisInterface,0x3); PDEBUG("InitInterrupt: 21555 interrupt enabled\n"); result=request_irq(pDE->IRQLine, interrupt_handler, SA_INTERRUPT | SA_SHIRQ, "cPCI6765", pDE); if(result) PWARN("InitInterrupt: ERROR Could not connect to interrupt.\n"); return ERR_INT_INIT;... -
Page 76: Driver Installation Procedures
B.3.6 Driver Installation Procedures Intel 21555 Sample Driver User Manual Introduction: This is a sample driver that enables the non-transparency PCI-to PCI bridge mode access and maps the memory to the other side of the bridge. We have configured its’ application as a ram disk, so no extra utilities are required. -
Page 77: Baseboard Management
Appendix C Baseboard Management The Zircon CP BMC is used to manage all aspects of system boards. The hardware features are summarized as follows. • ARM7/TDMI controller with internal 14KB SRAM • Six channels A-to-D converter for voltage monitoring, 10-bit resolution •... -
Page 78: Flash Organization
• Support SDR and sensor reading C.1.1 Flash Organization C.1.2 Host Interface The Host and system BIOS communicate with Zircon through the LPC-bus. Two software interface types are provided: • Keyboard Controller Style Interface (KCS) – The KCS interface model consists of a set of two registers. One of the registers is the Data In/Out register. -
Page 79: Serial Eeproms
0x00E6 C.1.3 Serial EEPROMs The cPCI-6765 provides two serial EEPROMs to store the SEL and FRU information. Each SEL record uses 16 bytes so there are 500 records for SEL storage. The slave address for SEL is 0xAC. FRU is used to store the VPD data. - Page 80 C.1.4.1 Global Commands • GET DEVICE ID – Used to retrieve the intelligent device’s gerneral information. • COLD RESET – The firmware issues a reset pulse to reset itself and to generate a reset for FLASH memory. • WARM RESET - Zircon responds to this command by executing a cold reset.
- Page 81 • MASTER WRITE-READ I C – Zircon provides access to non-intelligent devices on the private I C bus and IPMB behind the management controller via the MASTER WRITEREAD I C command. C.1.4.3 Event Commands The ‘Sensor/Event’ Network Function is used for device functionality related to transmission, reception and handling of ‘Event Messages’...
- Page 82 • RESERVE SDR REPOSITORY – Sets the present “owner” of the repository, as identified by the “Software ID” or by the requesters Slave Address from the command. • GET SDR – Returns the sensor record specified by Record ID. • GET SDR REPOSITORY TIME –...
- Page 83 • CLEAR SEL – Clears all records from the SEL and provides status of the operation. • GET SEL TIME – Returns the time from the SEL device. • SET SEL TIME - Initializes the time in the SEL device. C.1.4.7 Chassis Commands •...
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Page 84: Sensor Data Record
C.1.5 Sensor Data Record The cPCI-6765 has pre-defines SDRs such as voltages, system temp. Sensor Sensor Normal Device Remark Number name Reading 0x20 Vcore 1 Zircon 1.15 0x21 Zircon 0x22 3.3V Zircon 0x23 Vcore 2 Zircon 1.15 0x24 Zircon 0x11... - Page 85 outside or remote. We can us e this command to archieve this goal. C.1.6.1 Dynamic IPMB address allocation ü Query current GA and I2C address Action Byte Code Description 0xC0 NetFn/LUN for OEM, 0 Request 0xF0 OEM defined command Complete Code 00 means OK IPMB address 0xB0-0xEC besides C2 is reserved Response...
- Page 86 ü Get Event Autoforward Status Action Byte Code Description 0xC0 NetFn/LUN for OEM , 0 Request 0x11 OEM defined command Respons Complete Code 00 means OK Current value Current control value C.1.6.3 Host System Reset This command will pull low the reset button for one second then put it back to high.
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Page 87: Warranty Policy
Warranty Policy Thank you for choosing ADLINK. To understand your rights and enjoy all the after-sales services we offer, please read the fo llowing carefully. Before using ADLINK’s products, please read the user manual and follow the instructions exactly. When sending in damaged products for repair, please attach an RMA application form. - Page 88 Customers are responsible for the fees regarding transportation of damaged products to our company or to the sales office. To ensure the speed and quality of product repair, please download application form from company website www.adlinktech.com. Damaged products with RMA forms attached receive priority.
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