Advanced Bring-Up With Base Targeted Reference Design - Xilinx Artix-7 FPGA AC701 Getting Started Manual

Advanced Bring-up with Base Targeted Reference Design

Introduction
Figure 14
Design (TRD) which delivers up to 10 Gb/s of performance per direction.
X-Ref Target - Figure 14
GUI
XRaw Driver
PCIe x4
Gen2 Link
XDMA
Driver
Block x4 Gen2
Integrated Blocks
Xilinx IP
in FPGA
Software Driver Custom RTL
The intent of this design is to demonstrate a high performance data transfer system using
the PCI Express® x4 GEN2 endpoint with a high performance scatter-gather packet DMA
controller from NorthWest Logic and DDR3 64-bit SODIMM memory operating at
800 Mb/s.
The PCIe® endpoint and DMA controller together are responsible for the movement of
data between a PC and an FPGA. S2C implies data movement from a PC to an FPGA and
C2S implies data movement from an FPGA to a PC. A DDR3 SDRAM (64-bit, 800 Mb/s or
400 MHz) is used for packet buffering — a virtual FIFO layer facilitates the use of DDR3
AC701 Getting Started Guide
UG967 (v4.0.1) March 05, 2014
depicts the block-level overview of the Artix-7 FPGA base Targeted Reference
XADC
Power and
UCD90120A
Temperature
Monitor
PCIe User Space
Monitor Registers
AXI Target
PCIe IP
Master
GTP
Transceiver
S2C0
C2S0
PCIe
Packet
Integrated
DMA
Endpoint
S2C1
C2S1
Third Party IP
On Board
Figure 14: Artix-7 FPGA Base TRD Block Diagram
www.xilinx.com
Advanced Bring-up with Base Targeted Reference Design
DDR3 IO
AXI MIG
512 bits at
100 MHz
AXI VFIFO
WR RD
512 bits at
100 MHz
64 x 250 MHz 64 x 250 MHz
AXIS IC
S0 S1 S2 S3 M3
128 bits at
125 MHz
128 bits at
125 MHz
AXI ST (128 bits at 125 MHz)
AXI MM (512 bits at 100 MHz)
64 bits at
800 Mb/s
DDR3
512 bits at
100 MHz
AXIS IC
M2 M1 M0
AXI Stream Generator
and Checker
Checker
128 bits at
125 MHz
Generator
Loopback
AXI Stream Generator
and Checker
Checker
128 bits at
125 MHz
Generator
Loopback
Control Path
50 MHz Domain
UG967_14_121912
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