Platform Features; The Platform Reference Design - Xilinx Kintex UltraScale KCU1500 User Manual

Sdaccel platform acceleration development board
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Platform Features

The features of the Kintex UltraScale KCU1500 Acceleration development board and the
Xilinx Acceleration KCU1500 4DDR Expanded Partial Configuration platform are intended
for use as a high-performance acceleration platform for the SDAccel Environment, as
follows:
Connectivity to the host computer uses the Xilinx DMA subsystem for PCI Express®
(PCIe), containing a Scatter-Gather DMA and PCI Express 3.x integrated bock. The
Kintex UltraScale KCU1500 Acceleration development board supports Gen3 x8
connectivity.
Four UltraScale Memory IP instances enable access to available DDR4 SDRAM. The
Kintex UltraScale KCU1500 Acceleration development board contains four channels of
DDR4-2400 SDRAM, at 4GB per channel for a total of 16GB global memory.
AXI SmartConnect IP provides high-performance AXI memory-mapped connectivity
among IP cores throughout the platform.
The SDAccel OpenCL Programmable Region IP core and its designated level of
hierarchy enable the platform to be used with the SDAccel System Compiler, C/C++,
OpenCL, and RTL user kernels.
Partitioning, clocking, and reset networks are designed to support the expanded partial
reconfiguration flow, including two independent frequency-adjustable kernel clock
sources.
SDx Environments application profiling using trace offload hardware infrastructure, and
for flash memory programming using SPI flash IP infrastructure are supported.

The Platform Reference Design

The platform reference design includes the necessary design sources, scripts, and
instructions to build the Xilinx Acceleration KCU1500 4DDR Expanded Partial Configuration
platform. The modular scripts are used with Vivado from the SDx Environments installation
to construct the IP integrator block diagram, synthesize the design, implement the design,
and produce a DSA file for use with the SDAccel Environment.
To modify and adapt the design, you must do the following steps:
1. Construct the IP integrator block diagram within Vivado.
2. Make the desired changes.
3. Continue with synthesis, implementation, and DSA creation.
Kintex UltraScale KCU1500 Acceleration Development Board
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 1: Overview
6
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