Advanced Bring-Up Using The Base Targeted Reference Design - Xilinx Kintex-7 FPGA KC705 Getting Started Manual

Advanced Bring-up Using the Base Targeted Reference Design

The primary components of the Kintex-7 FPGA Base TRD are:
•
•
•
The TRD system can sustain up to 10 Gb/s throughput end to end.
Figure 10
X-Ref Target - Figure 10
Software Hardware
Software
Driver
Interface Blocks in FPGA
Note:
indicate data flow directions.
KC705 Getting Started Guide
UG883 (v4.0.1) May 28, 2014
Advanced Bring-up Using the Base Targeted Reference Design
Integrated Endpoint block for PCI Express (PCIe). See 7 Series FPGAs Integrated Block
for PCI Express User Guide (UG477).
Northwest Logic Packet DMA
Multiport Virtual FIFO
provides an overview of the TRD.
Target Interface
AXI Master
64 x
250 MHz
Multi-Channel
DMA for PCIe
64 x
250 MHz
Xilinx IP
AXI-ST
Figure 10: Kintex-7 FPGA Base TRD Block Diagram
In Figure 10 the arrows indicate AXI interface directions (from master to slave). They do not
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[Ref 5]
Performance
User Space
Registers Monitor
VFIFO
Controller
250 MHz
VFIFO
Controller
SI SI
256 x
200 MHz
AXI
Interconnect
SI SI
VFIFO
Controller
250 MHz
VFIFO
Controller
Custom Logic Third Party IP
AXI-MM
Raw Packet Data Block
Checker
64 x
Generator
Multiport Virtual FIFO
64 x
1,600 Mb/s
AXI
DDR3
MIG
Generator
64 x
Checker
Raw Packet Data Block
On Board
UG883_10_121112
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