Intrinsyc Open-Q 820 User Manual page 44

Open-Q™ 820 (APQ8096) / 820Pro (APQ8096SG) µSOM Development Kit User Guide Version 1.4
Pin# CAM0 (J5)
33 MIPI_CSI0_LANE3
_N
34 GND
35 CCI_I2C_SDA1
(APQ_GPIO19)
36 CCI_I2C_SCL1
(APQ_GPIO20)
37 CAM_IRQ
(APQ_GPIO24)
38 CAM0_MCLK3
(APQ_GPIO13)
39 MB_ELDO_CAM0_
DVDD
40, MB_VREG_5P0
41 (DNP)
Install R10 to
access rail
Note: A connection from the camera connectors on the carrier board to the Intrinsyc
camera adapter board is established by a 41-pin cable assembly from JAE Electronics (part
number JF08R0R041020MA)
The following table shows the combinations of camera usage for different use cases
CSI PHY
CSI0
CSI 1
CSI 2
CAM1 (J4)
MIPI_CSI1_LANE3_
N
GND
CCI_I2C_SDA1
(APQ_GPIO19)
CCI_I2C_SCL1
(APQ_GPIO20)
CAM_IRQ (DNP)
(APQ_GPIO24)
Install R40 to access
signal
CAM1_MCLK3
(APQ_GPIO13)
MB_ELDO_CAM1_D
VDD
MB_VREG_5P0
Install R28 to access
rail
Table 3.8.20-2. MIPI CSI Camera Use Cases
Use case
Up to 4 lane One Camera of 4 lane or
One camera of 3 lane
One Camera of 2 lane
One Camera of 1 lane
Up to 4 lane One Camera of 4 lane or
One camera of 3 lane
One Camera of 2 lane
One Camera of 1 lane
Up to 4 lane One Camera of 4 lane or
2 x Camera of 1 lane each
Copyright Intrinsyc Technologies Corporation
CAM2 (J3)
MIPI_CSI2_LANE3_N
GND
CCI_I2C_SDA1
(APQ_GPIO19)
CCI_I2C_SCL1
(APQ_GPIO20)
CAM_IRQ (DNP)
(APQ_GPIO24)
Install R46 to access
signal
CAM2_MCLK3
(APQ_GPIO13)
MB_ELDO_CAM2_D
VDD
MB_VREG_5P0
Install R35 to access
rail
Comment
44
Description
Input. MIPI CSI0 / CSI1 /
CSI2 data lane 3
Ground
Output / Input. Connected
to APQ8096 GPIO19.
Default use is for camera
CCI1 I2C data interface
Output. Connected to
APQ8096 GPIO20. Default
use is for camera CCI1 I2C
clock interface
Input. Connected to
APQ8096 GPIO24.
CAM_IRQ signal
Output. Connected to
APQ8096 GPIO13. Default
N/C. Use is for secondary
camera master clock.
Maximum 24MHz
Power output. Connected
to U5, U6, and U71 AMS
LDO regulator. Default is
+1.2V. Maximum current
500mA
Power output. 5V Power
supply. Maximum 700mA