Intrinsyc Open-Q 820 User Manual page 43

Open-Q™ 820 (APQ8096) / 820Pro (APQ8096SG) µSOM Development Kit User Guide Version 1.4
Pin# CAM0 (J5)
13 CAM0_RST_N
(APQ_GPIO25)
14 CAM0_STANDBY_
N (APQ_GPIO26)
15 CCI_I2C_SCL0
(APQ_GPIO18)
16 CCI_I2C_SDA0
(APQ_GPIO17)
17 CAM_MCLK0_BUF
(APQ_GPIO13)
18 FLASH_STROBE_T
RIG
(APQ_GPIO22)
19 GND
20 MIPI_CSI0_LANE0
_N
21 MIPI_CSI0_LANE0
_P
22 GND
23 MIPI_CSI0_CLK_N
24 MIPI_CSI0_CLK_P
25 GND
26 MIPI_CSI0_LANE1
_N
27 MIPI_CSI0_LANE1
_P
28 GND
29 MIPI_CSI0_LANE2
_N
30 MIPI_CSI0_LANE2
_P
31 GND
32 MIPI_CSI0_LANE3
_P
CAM1 (J4)
Install R36 to access
signal
CAM1_RST_N
(APQ_GPIO104)
CAM1_STANDBY_N
(APQ_GPIO98)
CCI_I2C_SCL0
(APQ_GPIO18)
CCI_I2C_SDA0
(APQ_GPIO17)
CAM_MCLK1_BUF
(APQ_GPIO14)
FLASH_STROBE_T
RIG (DNP)
(APQ_GPIO22)
Install R37 to access
signal
GND
MIPI_CSI1_LANE0_
N
MIPI_CSI1_LANE0_
P
GND
MIPI_CSI1_CLK_N
MIPI_CSI1_CLK_P
GND
MIPI_CSI1_LANE1_
N
MIPI_CSI1_LANE1_
P
GND
MIPI_CSI1_LANE2_
N
MIPI_CSI1_LANE2_
P
GND
MIPI_CSI1_LANE3_
P
43
Copyright Intrinsyc Technologies Corporation
CAM2 (J3)
Install R42 to access
signal
CAM2_RST_N
(APQ_GPIO23)
CAM2_STANDBY_N
(APQ_GPIO133)
CCI_I2C_SCL0
(APQ_GPIO18)
CCI_I2C_SDA0
(APQ_GPIO17)
CAM_MCLK2_BUF
(APQ_GPIO15)
FLASH_STROBE_TR
IG (DNP)
(APQ_GPIO22)
Install R43 to access
signal
GND
MIPI_CSI2_LANE0_N
MIPI_CSI2_LANE0_P
GND
MIPI_CSI2_CLK_N
MIPI_CSI2_CLK_P
GND
MIPI_CSI2_LANE1_N
MIPI_CSI2_LANE1_P
GND
MIPI_CSI2_LANE2_N
MIPI_CSI2_LANE2_P
GND
MIPI_CSI2_LANE3_P
Description
Output. Connected to
APQ8096 GPIO25 /
GPIO104 / GPIO23.
Default use is for camera
reset
Output. Connected to
APQ8096 GPIO26 /
GPIO98 / GPIO133.
Default use is for camera
standby
Output. Connected to
APQ8096 GPIO18. Default
use is for camera CCI0 I2C
clock interface
Input / output. Connected
to APQ8096 GPIO17.
Default use is for camera
CCI0 I2C data interface
Output. Connected to
APQ8096 GPIO13 /
GPIO14 / GPIO15. Default
use is for camera master
clock. Maximum 24MHz
Output. Connected to
APQ8096 GPIO25. Default
use is for camera flash
strobe trigger
Ground
Input. MIPI CSI0 / CSI1 /
CSI2 data lane 0
Input. MIPI CSI0 / CSI1 /
CSI2 data lane 0
Ground
Input. MIPI CSI0 / CSI1 /
CSI2 clock lane
Input. MIPI CSI0 / CSI1 /
CSI2 clock lane
Ground
Input. MIPI CSI0 / CSI1 /
CSI2 data lane 1
Input. MIPI CSI0 / CSI1 /
CSI2 data lane 1
Ground
Input. MIPI CSI0 / CSI1 /
CSI2 data lane 2
Input. MIPI CSI0 / CSI1 /
CSI2 data lane 2
Ground
Input. MIPI CSI0 / CSI1 /
CSI2 data lane 3