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Renesas RA Family
RA0 Quick Design Guide
Introduction
This document answers common questions and points out subtleties of the RA0 MCU that might be missed
unless the hardware manual was extensively reviewed. The document is not intended to be a replacement
for the hardware manual. It is intended to supplement the manual by highlighting some key items most
engineers will need to start their own design. It also discusses some design decisions from an application
point of view.
Target Device
RA0 MCU Series
Contents
1.
Power Supplies ........................................................................................................................ 3
1.1
References .............................................................................................................................................. 3
2.
Emulator Support ..................................................................................................................... 4
2.1
SWD Interface ......................................................................................................................................... 4
3.
MCU Operating Modes ............................................................................................................ 5
4.
Option-Setting Memory ............................................................................................................ 6
4.1
Option-Setting Memory Registers ........................................................................................................... 7
5.
Clock Circuits ........................................................................................................................... 8
5.1
Reset Conditions ..................................................................................................................................... 9
5.2
Clock Frequency Requirements .............................................................................................................. 9
5.2.1
Requirements for Programming and Erasing ROM or Data Flash ........................................................ 9
5.3
Lowering Clock Generation Circuit (CGC) Power Consumption ............................................................. 9
5.4
Writing the System Clock Control Registers ......................................................................................... 10
5.5
Clock Setup Example ............................................................................................................................ 10
5.6
HOCO Accuracy .................................................................................................................................... 11
5.7
Flash Interface Clock ............................................................................................................................. 11
5.8
Board Design ......................................................................................................................................... 11
5.9
External Crystal Resonator Selection.................................................................................................... 11
5.10 External Clock Input .............................................................................................................................. 12
6.
Reset Requirements and the Reset Circuit ............................................................................ 12
6.1
Pin Reset ............................................................................................................................................... 12
6.2
Power-On Reset .................................................................................................................................... 13
6.3
Independent Watchdog Timer Reset ..................................................................................................... 13
6.4
Voltage-Monitoring Resets .................................................................................................................... 13
6.5
Software Reset ...................................................................................................................................... 13
R01AN7309EU0100 Rev.1.00
Apr.09.24
Application Note
Page 1 of 33
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Table of Contents
Related Manuals for Renesas RA0 Series
Summarization of Contents
Power Supplies
References
Lists documents for further information regarding power supply for the RA MCU Group.
Emulator Support
SWD Interface
Explains the typical connectivity of the debug interface when using Serial Wire Debug (SWD).
Option-Setting Memory
Option-Setting Memory Registers
Summarizes the Option-Setting Memory registers and their configuration importance before startup.
Clock Circuits
Reset Conditions
Describes the initial state of RA0 MCUs after reset, including the default main clock source.
Clock Frequency Requirements
Lists minimum and maximum frequencies for RA0 MCU internal clocks and their requirements.
Writing the System Clock Control Registers
Explains the correct procedure for writing to clock control registers when switching system clock sources.
External Crystal Resonator Selection
Guides the selection of external crystal resonators for RA0 MCUs based on design requirements.
Reset Requirements and the Reset Circuit
Pin Reset
Explains how the RES pin functions as a reset input and the procedure for resetting the MCU.
Power-On Reset
Describes the conditions that trigger a power-on reset (POR) and how the chip is released from it.
Independent Watchdog Timer Reset
Explains the internal reset generated by the Independent Watchdog Timer (IWDT) when it underflows.
Voltage-Monitoring Resets
Details how the MCU uses on-board comparators to protect against unsafe operation during brownouts via voltage monitoring.
Memory
SRAM
Lists the SRAM specifications for the RA0E1 MCU, including capacity, address, and access times.
On-Chip Flash Memory
Explains the two flash memory sections (code and data) in RA0 MCUs and their programming/erasure characteristics.
ID Code Protection
Details how to use a 128-bit ID code in option-setting memory to control access to the MCU via the on-chip debugger.
Restriction on Endianness
States that memory space must be little-endian for code execution on the Arm Cortex-M core.
I/O Port Configuration
Multifunction Pin Selection Design Strategies
Offers design strategies for selecting port functions when multiple peripheral functions are needed on RA0 MCUs.
Setting Up and Using a Port as GPIO
Details two methods for setting up and using a port as GPIO: Port Control Registers and PmnPFS registers.
Setting Up and Using Port Peripheral Functions
Guides on configuring port pin characteristics and selecting peripheral functions using PmnPFS registers.
Setting Up and Using IRQ Pins
Explains how to use port pins as hardware interrupt lines (IRQ) and configure their trigger detection.
Buses
Bus Error Monitoring
Explains how the monitoring system detects and reports bus errors, including illegal address access.
Bus Error Types
Lists the types of errors that can occur on each bus, specifically illegal address access.
Operation When a Bus Error Occurs
Details the operation when a bus error occurs, including error reporting and storage.
General Layout Practices
Digital Domain vs. Analog Domain
Discusses the separation of digital and analog domains and pin functions to avoid data errors.
High Speed Signal Design Considerations
Covers design considerations for high-speed digital signals and the influence of external stimuli.
Signal Group Selections
Explains how to select signal groups, including handling of suffixes on pin names for RA0 devices.
Need help?
Do you have a question about the RA0 Series and is the answer not in the manual?
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