Nintendo Ultra64 Programmer's Manual page 62

Vector Unit Instructions
Fmt S, T signed
1 1 0 uns, sign
1 1 1 sign, sign
1
MPEG1 Specification, ISO/IEC 11172-2. MPEG documentation is available from the American National
Standards Institute (ANSI), New York, N.Y.; or from the Japanese Industrial Standards Committee (JISC),
Tokyo, Japan.
62
Prod
Round Value
Shift
0 0
<< 16 0
vmulf and vmulu support operands with 15 fraction bits, and differ only in
whether the result is clamped signed or unsigned. Small integer operands
can be multiplied with vmudh (if the result is bigger than 16 bits, double
precision should be used.)
vmulq is intended specifically to support 12 bit MPEG inverse
1
quantization . The
upper accumulator. The round value (31<<16) is added to the product if the
product
is negative, otherwise zero is added. The result is clamped and
shifted right by 17 before being written to
producing a result from -2048 to 2047 aligned to the short MSB. In other
words,
VD = (ACC >> 17) & 0xFFF0
vmacq ignores the
accumulator by adding (32<<16) if the accumulator is negative and bit 21 is
zero, adding (-32<<16) if positive and bit 21 is zero, or adding zero if the
accumulator bits 47-21 is zero or bit 21 is one. The clamp and shift is the same
as vmulq.
vrnd is intended to specifically support MPEG DCT rounding
operand is conditionally added to the accumulator. For vrndn,
if the accumulator is negative, otherwise zero is added. For vrndp,
added if the accumulator is positive, otherwise zero is added.
left by 16 if the register number
is the instruction field
Result Clamping
b15-0 sign, b31-msb
b31-16 sign, b31-msb
product is shifted left by 16 in order to clamp on the
vs vt
and operands, and performs oddification
vs
is 1, or not shifted if
vs
, not the contents of
Instructions
vmudn, vmadn
vmudh, vmadh
vd and AND'd with 0xFFF0,
1
. The
vt
vt
is shifted
vs
is zero (note this
vs
).
1
of the
vt
is added
vt
is