Nintendo Ultra64 Programmer's Manual page 283

VMULF
31 26 25
COP2
0 1 0 0 1 0
6
Format:
vmulf vd, vs, vt
vmulf vd, vs, vt[e]
Description:
The 16-bit elements of vector register
elements of vector register
Bits 31...16 of the accumulator are clamped to 16 bit signed values and placed into vector register
vd
.
If an element specification
used as described below.
Revision 1.0
Vector Multiply
of Signed Fractions
24 21 20 16
1 e vt
1 4 5
vt
vs
, and loaded into the accumulator.
e
is present for vector register
15 11 10
vs vd
5 5
are multiplied on an element-by-element basis to the
vt
, the selected scalar element(s) of
VMULF
6 5 0
VMULF
0 0 0 0 0 0
6
vt
is
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