Nintendo Ultra64 Programmer's Manual page 167

BLTZ
31 26
REGIMM
0 0 0 0 0 1
6
Format:
bltz rs, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot
offset
and the 16-bit
have the sign bit set, then the program branches to the target address, with a delay of one
instruction.
Since the RSP program counter is only 12 bits, only 12 bits of the calculated address are used.
Operation:
target  (offset
T:
condition  (GPR[rs]
T+1: if condition then
PC
11...0
endif
Exceptions:
None
Revision 1.0
Branch On Less Than Zero
25 21 20
rs BLTZ
0 0 0 0 0
5 5
, shifted left two bits and sign-extended. If the contents of general register
14 2
) || offset || 0
15
= 1)
31
PC
+ target
11...0 11...0
16 15
offset
16
BLTZ
0
rs
167