Nintendo Ultra64 Programmer's Manual page 279

VMUDM
31 26
COP2
0 1 0 0 1 0
6
Format:
vmudm vd, vs, vt
vmudm vd, vs, vt[e]
Description:
The 16-bit elements of vector register
elements of vector register
mid partial product, multiplying an integer (
Bits 31...16 of the accumulator are clamped to 16 bit signed values and placed into vector register
vd
.
If an element specification
used as described below.
Revision 1.0
Vector Multiply
of Mid Parital Products
25 24 21 20
1 e vt
1 4 5
vs
, and loaded into the accumulator. This instruction is designed for the
e
is present for vector register
16 15 11 10
vs vd
5
vt
are multiplied on an element-by-element basis to the
vs
) times a fraction (
vt
, the selected scalar element(s) of
VMUDM
6 5 0
VMUDM
0 0 0 1 0 1
5 6
vt
).
vt
is
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