Nintendo Ultra64 Programmer's Manual page 121

Revision 1.0
<vRegsRegOp> <vectorRegister>
<expression>
<sRegvRegOp> <scalarRegister>
<sRegvRegOp> <scalarRegister>
<element>
<noOperandOp>

<vectorInstruction>
<vectorRegister>
<veRegvRegvRegOp> <vectorRegister>
<vectorRegister>
<vdRegvRegOp> <vectorRegister>
<vectorRegister>
 jr
<regOp>
 add
<regRegRegOp>
|
 lui
<regImmOp>
 addi
<regRegImmOp>
xori
 bgez
<regOffsetOp>
 beq
<regRegOffsetOp>
 lb
<regOffsetBaseOp>
 sll
<regRegShiftOp>
 sllv
<sregRegRegOp>
BNF Specification of the RSP Assembly Language
<element>
[
<scalarRegister>
(
<vectorRegister> |
,
<vectorRegister>
,
|
]
<veRegvRegvRegOp> <vectorRegister>
<vectorRegister> |
,
<element>
[
[
<element>
[
| | | |
addu and nor
|
subu xor
| | |
addiu andi ori
| | |
bgezal bgtz blez
|
bne
| | | |
lbu lw lh lhu
| |
sra srl
| |
srav srlv
] ,
|
)
[
,
<vectorRegister>
, ,
|
]
<element>
] ,
]
| | |
or slt sltu sub
| | |
slti sltiu
| |
bltz bltzal
| | |
sb sh sw
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