Nintendo Ultra64 Programmer's Manual page 179

LBV
31 26
LWC2
1 1 0 0 1 0
6
Format:
lbv vt[element], offset(base)
Description:
This instruction loads a byte (8 bits) from the effective address of DMEM into byte
vt
register .
The effective address is computed by adding the
GPR).
This instruction has three load delay slots (results are available in the fourth instruction following
this load). If an attempt is made to use the target register
interlocking will stall the processor until the load is completed.
Note:
ordinal element count, as in VU computational instructions.
Operation:

T:
Addr ((offset
VR[vt][element]
Exceptions:
None
Revision 1.0
Load Byte
into Vector Register
25 21 20 16
base vt
5 5
element
The element specifier
16
) || offset ) + GPR[base]
15 15...0
 dmem[Addr
7...0
15 11 10
LBV element
0 0 0 0 0
5 4
offset
to the contents of the
vt
in a delay slot, hardware register
is the byte element of the vector register, not the
]
11...0 7...0
LBV
7 6 0
offset
7
e
of vector
base
register (a SU
179