Nintendo Ultra64 Programmer's Manual page 306

VRNDN
31
COP2
0 1 0 0 1 0
6
Format:
vrndn vd, vs, vt
vrndn vd, vs, vt[e]
Description:
This instruction is specifically designed to support MPEG DCT rounding.
The vector register
instruction field bits) and conditionally added to the accumulator. If the accumulator is negative,
vt
is added, otherwise zero is added.
If an element specification
used as described below.
306
Vector Accumulator
DCT Rounding (Negative)
26 25 24 21 20
1 e
1 4
vt
is shifted left 16 bits if the
e
is present for vector register
16 15 11 10
vt vs
5 5
vs
field is 1 (not the contents of
VRNDN
6 5
vd VRNDN
0 0 1 0 1 0
5 6
vt
, the selected scalar element(s) of
0
vs vs
, but the
vt
is