Nintendo Ultra64 Programmer's Manual page 224

SRV
31
SWC2
1 1 1 0 1 0
6
Format:
srv vt[e], offset(base)
Description:
This instruction stores a vector register from byte element (16 - (address & 15)) to 15, to the 128 bit
aligned boundary up to the byte address, that is (address & ~15) to (address - 1). See Figure 3-2,
"Long, Quad, and Rest Loads and Stores," on page 51. A SRV with a byte address of zero writes no
bytes.
The effective address is computed by adding the
GPR).
Operation:

T:
Addr ((offset
data  VR[vt][0]
StoreDMEM (QUADWORD, data, Addr
Exceptions:
None
224
Store Quad (Rest)
from Vector Register
26 25 21 20
base
5
The element specifier
Note:
element count, as in VU computational instructions.
16
) || offset
15
127...0
16 15 11
vt SRV
0 0 1 0 1
5 5
offset
e
is the byte element of the vector register, not the ordinal
) + GPR[base]
15...0
)
11...0
SRV
10 7 6
element offset
4 7
base
to the contents of the
0
register (a SU