Nintendo Ultra64 Programmer's Manual page 225

SSV
31 26
SWC2
1 1 1 0 1 0
6
Format:
ssv vt[element], offset(base)
Description:
This instruction stores a half word (16 bits) from a vector register
The effective address is computed by adding the
GPR).
Note:
ordinal element count, as in VU computational instructions.
Operation:

T:
Addr ((offset
data  VR[vt][element]
StoreDMEM (HALFWORD, data, Addr
Exceptions:
None
Revision 1.0
Store Short
from Vector Register
25 21 20 16
base vt
5 5
element
The element specifier
16
) || offset ) + GPR[base]
15 15...0
15...0
15 11 10
SSV element
0 0 0 0 1
5 4
offset
to the contents of the
is the byte element of the vector register, not the
)
11...0
SSV
7 6 0
offset
7
vt
into DMEM.
base
register (a SU
225