Nintendo Ultra64 Programmer's Manual page 277

VMUDL
31 26 25
COP2
0 1 0 0 1 0
6
Format:
vmudl vd, vs, vt
vmudl vd, vs, vt[e]
Description:
The 16-bit elements of vector register
elements of vector register
instruction is designed for the low partial product, multiplying a fraction (
Bits 15...0 of the accumulator are clamped to 16 bit signed values and placed into vector register
If an element specification
used as described below.
Revision 1.0
Vector Multiply
of Low Parital Products
24 21 20 16
1 e vt
1 4 5
vt
vs,
shifted down by 16, and loaded into the accumulator. This
e
is present for vector register
15 11 10
vs vd
5 5
are multiplied on an element-by-element basis to the
vt
, the selected scalar element(s) of
VMUDL
6 5 0
VMUDL
0 0 0 1 0 0
6
vs
) times a fraction (
vt
).
vd
.
vt
is
277