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Nintendo Ultra64 manual available for free PDF download: Programmer's Manual
Nintendo Ultra64 Programmer's Manual (331 pages)
RSP
Brand:
Nintendo
| Category:
Computer Hardware
| Size: 1.33 MB
Table of Contents
Table of Contents
3
1 Introduction
15
Document Description
16
What It Is
16
What It Is Not
16
Information Presentation
17
RSP Software Development Tools
19
Rspasm
19
Cpp
20
Buildtask
21
Rsp2Elf
21
Rsp, Rspg
21
Gameshop Debugger (Gvd)
22
2 RSP Architecture
23
Overview
24
Slave to the CPU
24
Part of the RCP
24
R4000 Core
25
Figure 2-1 Block Diagram of the RCP
25
Clock Speed
26
Vector Processor
26
Major R4000 Differences
27
Pipeline Depth
27
No Interrupts, Exceptions, or Traps
27
Coprocessors
27
Missing Instructions
27
Modified Instructions
28
Imem
29
Addressing
29
Explicitly Managed
29
Dmem
30
Addressing
30
Explicitly Managed Resource
30
External Memory Map
31
Scalar Unit Registers
32
SU Register Format
32
Register 0
32
Register 31
32
Figure 2-2 SU Register Format
32
SU Control Registers
33
Vector Unit Registers
34
VU Register Format
34
VU Register Addressing
34
Computational Instructions
34
Loads, Stores, and Moves
35
Accumulator
36
VU Control Registers
36
Vector Compare Code Register (VCC)
36
Figure 2-4 VU Accumulator Format
36
Vector Carry out Register (VCO)
37
Figure 2-5 VCC Register Format
37
Figure 2-6 VCO Register Format
37
Vector Compare Extension Register (VCE)
38
Figure 2-7 VCE Register Format
38
SU and VU Interaction
39
Dual Issue of Instructions
39
RSP Instruction Set
40
Instruction Formats
40
SU Instruction Format
40
VU Instruction Format
40
Distinguishing SU and VU Instructions
40
Illegal Instructions
40
Execution Pipeline
41
RSP Block Diagram
41
Figure 2-8 RSP Block Diagram
42
Mary Jo's Rules
43
Register Hazards
43
SU Is Bypassed
44
Figure 2-9 Pipeline Bypassing
44
Coprocessor 0
45
Interrupts, Exceptions, and Processor Status
46
Interrupts
46
Exceptions
46
Processor Status
46
3 Vector Unit Instructions
47
VU Loads and Stores
48
Figure 3-1 VU Load and Store Instruction Format
48
Table 3-1 VU Load/Store Instruction Summary
49
Normal
50
Figure 3-2 Long, Quad, and Rest Loads and Stores
51
Packed
52
Figure 3-3 Packed Loads and Stores
53
Figure 3-4 Packed Load and Store Alignment
54
Transpose
54
Figure 3-5 Transpose Loads and Stores
55
VU Register Moves
56
Figure 3-6 VU Coprocessor Moves
56
VU Computational Instructions
57
Figure 3-7 VU Computational Instruction Format
57
Table 3-2 VU Computational Instruction Opcode Encoding
57
Table 3-3 VU Computational Instruction Element Encoding
58
Using Scalar Elements of a Vector Register
58
Figure 3-8 Scalar Half and Scalar Quarter Vector Register Elements
59
VU Multiply Instructions
61
Figure 3-9 VU Multiply Opcode Encoding
61
Table 3-4 VU Multiply Instruction Summary
61
Figure 3-10 Double-Precision VU Multiply
64
Vector Multiply Examples
64
VU Add Instructions
67
Figure 3-11 VU Add Opcode Encoding
67
Table 3-5 VU Add Type Encoding
67
Vector Add Examples
68
VU Select Instructions
70
Figure 3-12 VU Select Opcode Encoding
70
Table 3-6 VU Select Type Encoding
70
Vector Select Examples
73
VU Logical Instructions
74
Figure 3-13 VU Logical Opcode Encoding
74
Table 3-7 VU Logical Type Encoding
74
VU Divide Instructions
75
Figure 3-14 VU Divide Opcode Encoding
75
Table 3-8 VU Divide Type Encoding
75
Table 3-9 VU Divide Instruction Summary
76
Reciprocal Table Lookup
77
Higher Precision Results
78
Vector Divide Examples
78
4 RSP Coprocessor 0
81
Register Descriptions
82
RSP Point of View
82
Table 4-1 RSP Coprocessor 0 Registers
82
C2, $C3
83
Figure 4-1 DMA Transfer Length Encoding
84
Table 4-2 RSP Status Register
85
Table 4-3 RSP Status Write Bits
86
C10
89
C11
90
Table 4-4 RDP Status Register
90
Table 4-5 RSP Status Write Bits (CPU VIEW)
91
C12
92
C13
92
C14
93
C15
93
CPU Point of View
93
Table 4-6 RSP Coprocessor 0 Registers (CPU VIEW)
94
Other RSP Addresses
95
Table 4-7 Other RSP Addresses (CPU VIEW)
95
Dma
96
Alignment Restrictions
96
Timing
96
DMA Full
96
DMA Wait
96
DMA Addressing Bits
97
CPU Semaphore
97
DMA Examples
97
Figure 4-2 DMA Read/Write Example
98
Figure 4-3 DMA Wait Example
99
Controlling the RDP
100
How to Control the RDP Command FIFO
100
Examples
101
Figure 4-4 RDP Initialization Using the XBUS
101
Figure 4-5 Outputopen Function Using the XBUS
102
Figure 4-6 Outputclose Function Using the XBUS
103
5 RSP Assembly Language
105
Different from Other MIPS Assembly Languages
106
Why
106
Major Differences from the R4000 Instruction Set
106
Syntax
107
Tokens
107
Identifiers
107
Constants
107
Operators
108
Comments
108
Program Sections
109
Labels
109
Keywords
109
Expressions
110
Expression Operators
110
Table 5-1 Expression Operators
110
Precedence
111
Expression Restrictions
111
Table 5-2 Expression Operator Precedence
111
Registers
112
Vector Register Element Syntax
112
Program Statements
113
Assembly Directives
114
Align
114
Bound
114
Byte
115
Data
115
Dmax
115
End
116
Ent
116
Half
116
Name
116
Print
117
Space
117
Symbol
117
Text
117
Unname
118
Word
118
BNF Specification of the RSP Assembly Language
119
6 Advanced Information
125
DMEM Organization and Usage
126
Jump Tables
126
Constants
126
Labels in DMEM
127
Dynamic Data
127
Diagnostic Information
127
Performance Tips
128
Dual Execution
128
Vectorization
128
Software Pipelining
130
Loop Inversion
131
Loop Unrolling
132
Program Flow of Control
132
Profiling RSP Code
133
Figure 6-1 Real-Time Clock Watching on the RSP
134
Microcode Overlays
135
Memory System Implications
135
Entirely up to You
135
RSP Assembler Tricks
136
A Sample RSP Linker
136
Overlay Example
138
Overlay Makefile
138
Overlay DMEM Initialization
139
Overlay Initialization Code
140
Overlay Decision Code
141
Overlay DMA Code
141
Controlling the RSP from the CPU
142
Starting RSP Tasks
142
RSP Boot Microcode
142
Hidden os Functions
143
Microcode Debugging Tips
145
RSP Yielding
147
Requesting a Yield
148
Checking for Yield
148
Yielding
148
Saving a Yielded Process
149
Restarting a Yield Process
149
RSP Instruction Set Details
151
Table A-1RSP Instruction Operation Notations
152
Instruction Notation Examples
153
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