Nintendo Ultra64 Programmer's Manual page 189

LQV
31 26
LWC2
1 1 0 0 1 0
6
Format:
lqv vt[0], offset(base)
Description:
This instruction loads a byte-aligned quad word (128 bits) from the effective address of DMEM up
to the 128 bit boundary, that is (address) to ((address & ~15) + 15), into vector register
at byte element 0 up to (address & 15). The remaining portion of the quad word can be loaded with
the appropriate LRV instruction. See Figure 3-2, "Long, Quad, and Rest Loads and Stores," on
page 51.
The effective address is computed by adding the
GPR).
This instruction has three load delay slots (results are available in the fourth instruction following
this load). If an attempt is made to use the target register
interlocking will stall the processor until the load is completed.
TOperation:

T:
Addr ((offset
VR[vt][0]
127...0
Exceptions:
None
Revision 1.0
Load Quad
into Vector Register
25 21 20 16
base vt
5 5
16
) || offset ) + GPR[base]
15 15...0
 dmem[Addr
11...0
15 11 10
LQV 0
0 0 1 0 0
5 4
offset
to the contents of the
vt
in a delay slot, hardware register
]
127...0
LQV
7 6 0
offset
7
base
register (a SU
vt
starting
189