Nintendo Ultra64 Programmer's Manual page 180

LDV
31
LWC2
1 1 0 0 1 0
6
Format:
ldv vt[element], offset(base)
Description:
This instruction loads a double (64 bits) from the effective address of DMEM into vector register
starting at byte
The effective address is computed by shifting the
of the
offset
The
bit, so the offset used in the source code must be a multiple of 8 bytes.
This instruction has three load delay slots (results are available in the fourth instruction following
this load). If an attempt is made to use the target register
interlocking will stall the processor until the load is completed.
Operation:

T:
Addr ((offset
VR[vt][element]
Exceptions:
None
180
into Vector Register
26 25 21
base
5
e .
base register (a SU GPR).
field of the instruction is encoded by shifting the offset used in the source code down 3
The element specifier
Note:
ordinal element count, as in VU computational instructions.
13
) || offset
15
 dmem[Addr
63...0
Load Double
20 16 15 11
vt LDV
0 0 0 1 1
5 5
offset
element
is the byte element of the vector register, not the
3
|| 0 ) + GPR[base]
15...0
]
11...0 63...0
LDV
10 7 6
element offset
4 7
up by 3 bits and adding it to the contents
vt
in a delay slot, hardware register
0
vt