Nintendo Ultra64 Programmer's Manual page 192

LTV
31
LWC2
1 1 0 0 1 0
6
Format:
ltv vt[element], offset(base)
Description:
This instruction loads an aligned 128 bit memory word into a group of 8 vector registers, scattering
this memory word into a diagonal vector of shorts in 8 VU registers. The VU register number of
each slice is computed as (VT & 0x18) | ((Slice + (Element >> 1)) & 0x7) , which is to say that
specifies the beginning of an 8 register group.
The effective address is computed by adding the
GPR).
This instruction has three load delay slots (results are available in the fourth instruction following
this load). If an attempt is made to use the target register
interlocking will stall the processor until the load is completed.
Operation:
See "Transpose" on page 54.
Exceptions:
None
192
Load Transpose
into Vector Register
26 25 21 20
base
5
The element specifier
Note:
ordinal element count, as in VU computational instructions.
16 15 11 10
vt LTV
0 1 0 1 1
5 5
offset
to the contents of the
element
is the byte element of the vector register, not the
LTV
7 6
element offset
4 7
base
vt
in a delay slot, hardware register
0
vt
register (a SU